Advanced packaging (3D and chiplets)

Which is a basic advantage of 3D packaging, which stacks chips vertically?

  1. AInterconnects between chips become shorter, enabling higher speed, lower power and a smaller footprint
  2. BChips cool more easily
  3. CThe manufacturing process becomes simpler and cost always falls
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Answer: A. Interconnects between chips become shorter, enabling higher speed, lower power and a smaller footprint

Compared with placing chips side by side and connecting them through package substrate wiring, stacking them vertically makes the distance between chips very short. Signal delay and the power of charging and discharging wires shrink, many connections become easier to provide, and the footprint becomes smaller. On the other hand, heat tends to build up and processing becomes more complex.

  • A. Correct. Shorter interconnects are the biggest advantage.
  • B. Stacking makes heat build up more easily.
  • C. Processing becomes more complex, and cost does not necessarily fall.
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More Advanced packaging (3D and chiplets) questions

  1. What is the problem called in which the speed of supplying data from memory cannot keep up with improvements in processor compute performance, limiting overall performance?
  2. Which stacking method, long used in smartphone memory and elsewhere, stacks multiple chips slightly offset from one another and connects each to the substrate with wire bonding?
  3. In contrast to chiplets, what is the conventional approach called in which all the functions a system needs are built into one large chip?
  4. Advanced packaging steps that use front-end-like fine processing at the wafer level, such as forming TSVs and fine redistribution layers, sit between the front end and back end. What are they called?
  5. Which TSMC 2.5D packaging technology is widely used to place AI GPUs and HBM side by side on a silicon interposer and connect them?