Advanced packaging (3D and chiplets)

What is the wiring layer called that is formed on a chip or wafer surface to route electrode positions to the positions of external terminals?

  1. ARedistribution layer (RDL)
  2. BSTI
  3. CBuried oxide (BOX layer)
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Answer: A. Redistribution layer (RDL)

A redistribution layer (RDL) routes wiring from the chip's bond pads to where external terminals such as solder balls are to be placed. It is used in wafer-level packages, fan-out packages, interposers and more, and its wiring is becoming ever finer.

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More Advanced packaging (3D and chiplets) questions

  1. Which approach, instead of a large silicon interposer, embeds small pieces of silicon only at the chip-to-chip connection areas to achieve high-density wiring?
  2. Which is a correct advantage of glass substrates, being considered in place of organic materials for next-generation large package substrates?
  3. What is the technology called that mounts optical transceiver components close to switch ICs and the like in the same package, shortening electrical wiring to reduce power?
  4. Among hybrid bonding methods, which allows only chips judged good in test to be selected and bonded to the target wafer?
  5. What are the bumps called, far smaller than ordinary solder balls, used to connect chips stacked with TSVs and to connect chips to interposers?