Advanced packaging (3D and chiplets)

Which is especially likely to be a challenge in 3D packaging, which stacks chips vertically?

  1. AWiring becomes too long
  2. BChips are too light to secure
  3. CTemperature rise from heat generated by stacked chips, and removing that heat
Show answer and explanation

Answer: C. Temperature rise from heat generated by stacked chips, and removing that heat

3D packaging has the advantage of shorter wiring, but because heat-generating chips are stacked, heat tends to build up and is hard to remove from the inner chips. Higher temperatures degrade performance and reliability, so thermal design is an important challenge.

Practice this topic Back to topic

More Advanced packaging (3D and chiplets) questions

  1. Which correctly describes SiP (system in package)?
  2. In flip-chip connections, what is the main advantage of using copper pillars (Cu pillars) instead of solder balls?
  3. What is the wiring layer called that is formed on a chip or wafer surface to route electrode positions to the positions of external terminals?
  4. Which approach, instead of a large silicon interposer, embeds small pieces of silicon only at the chip-to-chip connection areas to achieve high-density wiring?
  5. Which is a correct advantage of glass substrates, being considered in place of organic materials for next-generation large package substrates?