Advanced packaging (3D and chiplets)

Why does panel-level packaging (PLP) gain more advantage over round wafers as packages get larger?

  1. ALarger packages make panels warp less
  2. BLarger packages no longer need fine redistribution layers
  3. CThe larger the package, the larger the fraction of edge area on a round wafer that cannot hold a package, whereas a rectangular panel can be filled almost to its edges
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Answer: C. The larger the package, the larger the fraction of edge area on a round wafer that cannot hold a package, whereas a rectangular panel can be filled almost to its edges

When rectangular packages are laid out on a round wafer, regions near the edge cannot hold a whole package, and the fraction grows with package size. Panel-level packaging (PLP) uses rectangular panels, so even packages tens of millimeters on a side can be laid out with little waste, and a 600 mm square panel has about 5 times the area of a 300 mm wafer. This is why PLP is being developed to cut the cost of large AI packages carrying many chiplets and HBM stacks. Warpage, die shift and uniformity over large areas become harder, however.

  • A. Warpage tends to worsen with panel size; it is not the reason.
  • B. Wiring-density requirements do not depend on package size, and fine wiring is actually harder on panels.
  • C. Correct. The difference in edge waste matters more for larger packages.
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More Advanced packaging (3D and chiplets) questions

  1. Which correctly describes chiplets?
  2. Which correctly describes a TSV (through-silicon via)?
  3. Which correctly describes HBM (High Bandwidth Memory)?
  4. Which correctly describes the role of the silicon interposer used in 2.5D packaging?
  5. Which correctly describes hybrid bonding?

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