What Is a Chiplet? Why Chips Are Split Into Smaller Dies
A chiplet design splits the circuits of a big chip into several smaller chips. Each is made separately, and they are connected inside one package. The bigger a chip is, the more of them come out faulty, so big chips cost more. There is also a limit to how big a chip can be made. That is why AMD, Intel, Apple, NVIDIA and others use chiplets. But the joins between chips cost extra power and time, so splitting does not always pay off.
What you'll learn
- Why one large chip is expensive, and the limit on how big a chip can be
- Three things you gain by splitting a chip into chiplets
- How chips are connected to each other (substrate, silicon bridges, stacking), and the UCIe standard
- The extra costs that splitting brings, and real examples from AMD, Intel, Apple and NVIDIA
Prerequisites: it helps to know that a chip (an integrated circuit) is "a circuit whose parts and wiring are built on one small piece of silicon." "What Is an Integrated Circuit?" explains this.
Where you see it: chiplets in the news
"The new CPU uses a chiplet design." "Two chips work together as one GPU." You see phrases like these in news about PC processors and AI GPUs. Both mean the same thing: one product contains several chips.
For example, NVIDIA announced its B200 AI GPU in 2024. It runs two large chips as one GPU. Apple's M1 Ultra, announced in 2022, is also two chips joined together.
The main chip in a smartphone, on the other hand, is still mostly made as one single chip as of 2026. Chiplets tend to pay off for big chips, not small ones.
First, some words: die, monolithic, chiplet
Chips are made many at a time on a round silicon plate called a wafer. At the end, the wafer is cut into separate pieces. Each cut piece of silicon is called a "die." In the news, "chip" can mean the die, or the finished, packaged product.
To become a product, a die goes into a case with pins or pads that connect it to the outside. This case is called a package. "How Are Chips Made?" explains the steps.
When all the circuits a product needs are put on one die, the design is called "monolithic." The word means "made of a single stone." Most chips are made this way.
The other way is to split the circuits across several dies. They are made separately, then connected inside one package to form one product. Each of these smaller dies is called a chiplet. Intel calls the same thing a "tile."
How it works 1: bigger dies mean more bad dies
Even in the cleanest factory, tiny specks of dust and scratches land on the wafer. They are too small to see. These are called defects. If a defect lands on an important part of a circuit, that die does not work correctly. It becomes a reject.
The share of good products among all those made is called yield. If defects land in random places, a die with a larger area is more likely to be hit. So the bigger the die, the lower the yield.
Let's try some numbers. Assume that defects that cause failures land at random, 0.1 per cm² on average. Then a 200 mm² (2 cm²) die has about an 82% chance of getting no defect at all. This comes from a probability calculation.
What about a die four times larger, at 800 mm²? Think of it as four 200 mm² areas side by side. All four areas must be free of defects. So multiply 0.82 by itself four times, which gives about 45%. Fewer than half are good.
Now split the same area into four 200 mm² dies. About 82% of them are good. Testing picks out the good ones, and only those are combined. Compare the same amount of silicon: enough for 100 large dies. You get about 45 good large dies. With small dies, you can build about 80 products of four dies each.
This comparison leaves some things out, though. It ignores the extra area of the circuits that link the dies. It also ignores the cost of testing and assembly, and failures during assembly. Counting these, the gap gets smaller.
What we used here is the simplest way of thinking, called the Poisson yield model. We also ignored dies that are cut off at the wafer's edge, and defects that occur in clusters. To try other numbers, use the die per wafer and yield calculator.
How it works 2: a limit on how much can be printed at once
Die size runs into a second wall. Circuit patterns are made by a machine that uses light to copy a master pattern onto the wafer. This machine is called a lithography tool. "What Is EUV Lithography?" explains it in detail.
A lithography tool does not print the whole wafer at once. It prints an area of fixed size, then moves and prints again, dozens of times. On widely used tools, the largest area one shot can print is 26 mm × 33 mm, about 858 mm² (ASML's tool specs).
A single die normally has to fit inside this area. So about 858 mm² is a rough upper limit on the size of one die. The master pattern is called a reticle, so this limit is also called the "reticle limit."
NVIDIA's B200 joins two dies, each as large as this limit allows. The circuits did not fit on one die, so they were split across two. Note that on a newer generation of EUV tools, called High-NA, the area per shot is halved, to 26 mm × 16.5 mm.
How it works 3: three things you gain by splitting
1. Better yield
The first gain is the yield we just looked at. With small dies, a defect costs you only that one die. This assumes each die has been checked as good before assembly (more on this later).
2. Choosing the process generation for each part
Chipmaking technologies have generation names such as "7 nm" and "3 nm." Newer generations can make finer circuits, but each wafer also costs more. "What Does 2nm or 3nm Mean?" explains what the numbers mean.
A chip has circuits that exchange data with parts outside it. These are called I/O (input/output) circuits. I/O circuits do not shrink much in a newer generation. So there is little to gain from making them in an expensive one.
AMD used this idea in 2019, in the second generation of its EPYC server CPUs (code-named Rome). It made up to eight compute dies in 7 nm, the leading-edge generation at the time. It made only one I/O die, in an older, cheaper 14 nm generation.
3. Reusing the same die
Combine different numbers of the same compute die, and you get several products with different performance. AMD used the same compute die from the second-generation EPYC in its Ryzen 3000 series for PCs. Fewer kinds of new dies need to be designed, which saves development time and money.
How it works 4: how the dies are connected
The split dies are joined by many wires. The more wires there are, and the shorter they are, the more data they can send using less power. There are three main ways to connect them.
Wiring in the substrate
The simplest way is to place the dies on the package's base board, called the package substrate. The wiring inside this board connects them. The board is made of resin and is cheap to make. But its wires are thick, so only a limited number fit. The second-generation EPYC is connected this way.
A silicon plate or bridge
When more wires are needed, a piece of silicon goes under the dies. Its fine wiring is made the same way as a chip's. When the dies sit side by side on a large silicon plate, the plate is called an interposer. Interposers often link AI GPUs to their memory, as "What Is HBM?" explains.
Apple says the two dies of the M1 Ultra are joined by a silicon go-between plate. It connects more than 10,000 signals. Apple calls this "UltraFusion" and says software sees it as one chip.
Another method skips the full plate. Instead, a small silicon bridge is embedded only under the edges where two dies meet. Intel calls this "EMIB" and has used it in volume production since 2017 (according to Intel's documents).
Placing dies side by side and joining them with fine wiring like this is called 2.5D packaging. The name means "halfway between laying chips flat (2D) and stacking them (3D)."
Stacking
Stacking dies on top of each other and connecting them vertically is called 3D packaging. The distance between the dies is very short. Connections can use the whole face of the die, so their number can grow greatly.
Stacked dies can also be joined without solder, by bonding copper contacts directly to each other. This is called hybrid bonding. AMD's Ryzen 7 5800X3D (released in 2022) uses this TSMC technology. A memory die is stacked on top of a compute die.
A common standard for linking dies: UCIe
In all the examples so far, one company designed the dies and joined them in its own way. To combine dies from different companies, everyone needs to follow the same rules for connecting them.
So in March 2022, ten large chip and IT companies announced a group to create a common standard. They included AMD, Arm, Intel, Samsung and TSMC. The standard is called UCIe. It sets how signals are sent between dies, and the steps for exchanging data.
A revised version, UCIe 2.0, was announced in August 2024. It added rules for stacked 3D packaging. Even with a shared standard, combining other companies' dies is still hard. Power delivery, heat and testing all remain challenges.
The extra costs of splitting
Chiplets are not all upside. Chip designers weigh the extra costs against the gains, then decide whether to split.
The joins cost power and time
Wiring inside one die can be very thin and short, and there can be a lot of it. Wires that cross between dies are longer, and there are fewer of them. So sending data across dies takes more power than sending it within one die.
The data also takes longer to arrive.
The linking circuits also take up die area. According to AMD, splitting the first EPYC (2017) into four dies added about 10% to the total silicon area. Even so, AMD estimated that the cost was only about 60% of one large die.
Testing before assembly is hard
If even one bad die gets in, the whole product is useless, along with the expensive good dies in it. So each die is checked as good before assembly. A die checked like this is called a KGD (known good die).
But a bare die, before packaging, is harder to test in detail than a finished product. The assembly step itself can also cause failures. Advanced assembly that uses interposers and similar parts is costly in its own right.
Heat builds up easily
Placing dies close together, or stacking them, gathers heat in a small space. In a stack, heat from the inner die can only escape by passing through the other dies. Removing heat is a major challenge, especially for 3D packaging.
Chiplets in real products
Here are the main examples, with the year each was announced or released. How the chip is split, and how the pieces are joined, differ from product to product.
| Year | Product | How it is split and joined |
|---|---|---|
| 2019 | AMD EPYC, 2nd generation (Rome) | Up to eight 7 nm compute dies and one 14 nm I/O die, joined on the substrate |
| 2022 | Apple M1 Ultra | Two dies joined by a silicon go-between plate (UltraFusion) |
| 2022 | AMD Ryzen 7 5800X3D | A memory die stacked on a compute die with hybrid bonding |
| 2023 | Intel Core Ultra (code-named Meteor Lake) | Four tiles stacked on a base die (Intel's Foveros technology) |
| 2024 | NVIDIA B200 | Two dies at the size limit, side by side, working as one GPU |
Intel's GPU code-named Ponte Vecchio (launched as a product in 2022) combines 47 tiles.
By the numbers
A TB (terabyte) is a trillion bytes. "X TB per second" is the amount of data that can be sent between dies in one second.
| Number | What it means |
|---|---|
| About 858 mm² | The largest area one exposure can print (26 mm × 33 mm). A rough upper limit on die size |
| About 45% and about 82% | Yield of 800 mm² and 200 mm² dies at 0.1 defects per cm² (this article's simplified calculation) |
| About 10% | Extra silicon area from splitting the first EPYC (2017) into four dies (AMD's figure) |
| Over 10,000; 2.5 TB per second | Number of signals linking the two M1 Ultra dies, and how much they can send (Apple, 2022) |
| 10 TB per second | How much the link between the two B200 dies can send (NVIDIA, 2024) |
| 47 | Number of tiles in Ponte Vecchio (Intel, 2022) |
The data rates are each company's announced figures. Companies may count them in different ways, so they cannot be compared directly.
Common misconceptions
Myth: Chiplets always make chips cheaper and faster
In fact, the gains come mainly for big chips. Splitting a small chip gives little yield gain. The cost of linking circuits and assembly often outweighs it. Data sent across dies also costs extra power and time. News stories tend to stress the benefits, so the costs are easy to miss.
Myth: "Chiplet" means 3D technology that stacks chips
In fact, a chiplet design is the idea of "make the parts separately and connect them in one package." Many products, such as the second-generation EPYC and the B200, place dies side by side. Stacking (3D packaging) is just one way of connecting them. People mix these up because "advanced packaging" and "3D" often appear in the same news stories.
Myth: With chiplets, we no longer need to make circuits smaller
In fact, compute dies are still often made in the leading-edge generation. The second-generation EPYC's compute dies used 7 nm, the leading edge at the time. Chiplets do not replace shrinking. They are a way to raise performance together with it. For the bigger picture, including other directions, see "Beyond Scaling."
Learn more
- Side by side vs. stacked, in a table: 2.5D vs. 3D packaging, Silicon interposer vs. organic interposer vs. silicon bridge
- Ways to bond stacked dies: Hybrid bonding vs. microbumps
- Testing before and after assembly: Wafer test vs. final test
- Try the numbers: the die per wafer and yield calculator lets you compare die sizes and defect counts
- Terms for the next step: chiplets in more depth, TSVs (vertical links through silicon), microbumps (tiny solder balls), and TSMC's CoWoS
- Related articles: "What Is HBM?" for stacked memory, and "What Is a Semiconductor Foundry?" for how work is split between companies that make dies and companies that assemble them