Advanced packaging (3D and chiplets)

Through the HBM3 generation, which is the data bus width per HBM stack?

  1. A1024 bits
  2. B8 bits
  3. C64 bits
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Answer: A. 1024 bits

Whereas a typical DDR DRAM module has a 64-bit data bus, HBM has a very wide 1024-bit bus per stack, achieving high bandwidth even though each line is not especially fast. That many wires cannot be routed on ordinary substrates, so high-density wiring such as a silicon interposer is required. The next generation, HBM4, widens it to 2048 bits.

  • A. Correct. A very wide bus yields high bandwidth.
  • B. 8 bits is a very narrow bus, the opposite of HBM's character.
  • C. 64 bits is the bus width of a typical DDR module.
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More Advanced packaging (3D and chiplets) questions

  1. When a TSV wafer is thinned to tens of micrometers and processed, which technique temporarily attaches it to a support wafer (carrier) to prevent cracking and warpage?
  2. In fan-out wafer-level packaging, what is the wafer-like form called that is rebuilt by placing diced chips with spacing on a support and embedding them in resin?
  3. Which is a challenge of moving to chiplets?
  4. What is the main aim of products that stack a cache SRAM chip on top of a processor chip with hybrid bonding?
  5. Which method is used to make silicon interposers larger than the maximum area a lithography tool can expose at once (about 26 mm × 33 mm)?