SOI vs Bulk Silicon: Differences for Chip Makers

Most chips are built directly in a plain silicon wafer, called bulk silicon. A silicon-on-insulator (SOI) wafer adds a thin layer of oxide buried under the thin silicon layer where the transistors sit. That insulating layer isolates the transistors from the substrate, which reduces parasitic capacitance and removes latch-up, so circuits can be faster or lower in power. The price is a more expensive wafer and poorer heat removal.

AspectBulk siliconSOI
StructureTransistors are made directly in the silicon waferA thin silicon layer sits on a buried oxide (BOX) on a silicon substrate
IsolationWells and shallow trench isolationComplete isolation from the substrate by the BOX, plus trench isolation sideways
Parasitic capacitanceLarger junction capacitanceSmaller, because the junctions sit on oxide
Latch-upPossible, because of parasitic thyristor structuresEliminated
Soft errorsMore sensitive to charge from radiationLess sensitive, because the charge-collection volume is small
Threshold tuningBody bias possible but limitedFully depleted SOI (FD-SOI) allows strong back-gate biasing through the BOX
Self-heatingHeat flows into the substrateWorse: the oxide layer conducts heat poorly
Wafer costLowSubstantially higher
Typical usesMost CMOS chips: memory, processors and general logicRF switches in smartphones, low-power FD-SOI chips for IoT and automotive, MEMS, high-voltage and radiation-tolerant ICs

Figures are typical orders of magnitude and vary by process generation and product.

When to use which

Bulk
The default for mainstream chips, because the wafers are cheap and the ecosystem is mature.
SOI
When low power, RF performance, radiation tolerance or body biasing is worth the extra wafer cost.

FAQ

What does the buried oxide do?

It insulates the thin silicon layer where the transistors sit from the substrate, which reduces parasitic capacitance and eliminates latch-up.

Why is SOI more expensive?

SOI wafers need extra manufacturing steps to create the buried oxide layer, so they cost substantially more than bulk wafers.

What is FD-SOI?

Fully depleted SOI uses a very thin silicon layer that is completely depleted of carriers. It gives good control of the channel and allows back-gate biasing through the buried oxide.

Why is self-heating worse in SOI?

The buried oxide conducts heat poorly, so heat from the transistors cannot escape into the substrate as easily as in bulk silicon.

Check your understanding

Which correctly describes the SOI (silicon on insulator) structure?

  1. AA transistor structure with no gate insulator
  2. BA structure in which transistors are built in a thin silicon layer on a buried oxide
  3. CA structure with two chips stacked
Show answer and explanation

Answer: B. A structure in which transistors are built in a thin silicon layer on a buried oxide

SOI builds transistors in a thin silicon layer on top of a buried oxide (BOX) within the wafer. Isolation from the substrate lowers junction capacitance and leakage and eliminates latch-up. SOI wafers are made by methods such as Smart Cut, which bonds an oxidized wafer to another and splits off a thin layer. SOI is widely used for RF switches (RF-SOI) and low-power FD-SOI logic.

What is an advantage of fully depleted SOI (FD-SOI) transistors?

  1. AThe silicon layer can be thick and heavily doped
  2. BNo gate electrode is needed
  3. CThe channel can be lightly doped, threshold voltage variation is reduced, and the threshold is easy to adjust with body bias
Show answer and explanation

Answer: C. The channel can be lightly doped, threshold voltage variation is reduced, and the threshold is easy to adjust with body bias

In FD-SOI, an extremely thin silicon layer of about 5–7 nm is fully depleted, so short-channel effects are controlled without channel doping and random-dopant variability is small. Applying voltage from the substrate through a thin buried oxide (about 20 nm) shifts the threshold dynamically, making FD-SOI attractive for low-voltage, low-power IoT, automotive and RF applications.

What is the cause of self-heating, which tends to be a problem in FinFETs and SOI transistors?

  1. AThe transistor gets too cold
  2. BNo current flows at all
  3. CThe channel is thin or surrounded by insulators, so heat generated cannot easily escape to the substrate
Show answer and explanation

Answer: C. The channel is thin or surrounded by insulators, so heat generated cannot easily escape to the substrate

Narrow structures like fins, or devices surrounded by low-thermal-conductivity oxide (SiO2 conducts about 1/100 as well as silicon), shed heat poorly to the substrate, so channels can run tens of degrees hotter than their surroundings. Higher temperature lowers mobility and current and accelerates electromigration in nearby wiring and device degradation, so it must be accounted for in reliability assessment and circuit design.

  1. In FinFETs built on bulk substrates, what is the purpose of a heavily doped layer at the base of the fin (the part the gate controls poorly)?
  2. Why are SOI wafers often used in MEMS fabrication?

Practice Advanced transistors (FinFET and GAA) questions

Key terms explained

SOI wafer
A wafer with a thin silicon layer on a buried oxide (BOX) layer over a silicon substrate. It is made, for example, by bonding a hydrogen-implanted wafer and splitting it. Its low parasitic capacitance suits FD-SOI devices and MEMS.
FD-SOI (fully depleted SOI)
Building transistors in a very thin silicon layer on buried oxide so the channel is fully depleted. The channel can be lightly doped, and body bias can tune the threshold voltage easily.

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