Advanced transistors (FinFET and GAA)
What is the main reason monolithic 3D integration can connect layers far more densely than 3D packaging that bonds separately made chips?
- AThe upper and lower layers are connected with solder bumps
- BThe layers are connected with optical interconnects
- CThe upper layer is built directly on the lower one and aligned by lithography, so layers can be connected with vias about the size of ordinary wiring vias
Show answer and explanation
Answer: C. The upper layer is built directly on the lower one and aligned by lithography, so layers can be connected with vias about the size of ordinary wiring vias
When chips or wafers are bonded, connection density is set by bonding alignment accuracy and connection size. In monolithic 3D integration, a thin semiconductor layer is formed or bonded on the first layer and the second transistor layer is made with lithographic alignment, so layers can be connected as finely as wiring vias. In exchange, the upper layer must be made at roughly 500 °C or below to avoid damaging the lower layer.
- A. Solder bumps have large pitches and are unsuited to dense connections.
- B. Layers are connected with ordinary metal vias.
- C. Correct. Alignment with lithographic accuracy is the reason.
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