What Does 2nm or 3nm Mean? Chip Process Nodes Explained
"2 nm" and "3 nm" are names for generations of the technology used to make chips. No part of the chip is actually 2 nm long. Long ago, the number roughly matched a size in the circuit. The two began to drift apart around the mid-1990s. Today the name means "we can pack things more tightly than the last generation."
What you'll learn
- How small 1 nanometer (nm) is
- What the node number used to measure, and why it drifted away from real sizes
- What actually gets smaller as generations advance
- Why "X nm" from different companies can't be compared directly
- The transistor shape used in the "2 nm class" (GAA)
Prerequisites: it helps to know that a transistor is a switch that turns on and off when a voltage is applied to its gate. "What Is a Transistor?" explains this.
In everyday life: "2 nm" in the news
"TSMC has started mass-producing 2 nm chips." "Rapidus is prototyping 2 nm chips in Hokkaido, Japan." Headlines like these have been common since around 2025. In 2023, Apple also introduced the A17 Pro, its chip for the iPhone 15 Pro, as "the industry's first 3-nanometer chip."
These numbers, "2 nm" and "3 nm," name a generation of chipmaking technology (the manufacturing process). In the industry, such a generation is called a process node, or simply a node. Normally, the smaller the number, the newer the generation.
So what is 2 nm the length of? Here is the short answer: today, it is not the length of any particular part. This article explains why, and how to read the numbers correctly.
How small is 1 nm?
The nanometer (nm) is a unit of length. 1 nm is one billionth of a meter, or one millionth of a millimeter. The US government's National Nanotechnology Initiative (NNI) says 1 nm is about how much a fingernail grows in one second.
According to the same source, a human hair is 80,000 to 100,000 nm thick, and a sheet of paper is about 100,000 nm thick. So nearly 100,000 nanometers fit across the width of one hair.
Let's also compare it with atoms. Silicon, the material of chips, is a crystal: its atoms are lined up in a regular pattern. The distance between the centers of neighboring atoms is about 0.235 nm. So 2 nm is only 8 to 9 atom spacings. The crystal is three-dimensional, so this count is only a rough guide.
Long ago, the number was a real length
A transistor has a part called the gate, which switches it on and off. The length of the gate, measured in the direction electrons flow, is called the gate length. A shorter gate makes the transistor smaller and lets it switch faster.
Inside a chip, the same shapes, such as wires, repeat over and over. The width of one line plus the gap to the next line is called the pitch. Half of it is called the half pitch. If lines and gaps are equally wide, the half pitch equals the width of one line.
In the 1970s and 80s, the number in a generation's name was about the same as its gate length or half pitch. It was a rough guide to "the narrowest line this generation can make." With each new generation, the number shrank to about 0.7 times the last one.
Why 0.7? Shrink both length and width to 0.7 times, and the area becomes 0.7 × 0.7, or about 0.5 times. So it was a rule of thumb for "the same circuit in about half the area." Later names followed this rule too: 0.35 µm, 0.25 µm, 0.18 µm, 0.13 µm, 90 nm, 65 nm, 45 nm and so on. The micrometer (µm) is 1,000 times larger than a nanometer, so 0.35 µm is 350 nm.
Why the number and real sizes drifted apart
IEEE, a society of electrical and electronics engineers, publishes a magazine called IEEE Spectrum. A 2020 article there explains that from the mid-1990s, gate length and wiring sizes began to shrink at different paces. To switch faster, companies shortened the gate length especially quickly. For example, in the generation called "130 nm," the gate length was 70 nm. In a 2021 announcement, Intel also said that names and gate lengths stopped matching in 1997.
Even so, the industry kept naming each generation about 0.7 times the last. So, step by step, the name stopped describing the size of any one feature.
In the 2010s, the gap grew even wider. If a flat transistor is made too small, current tends to leak even when the gate turns it off. So a new shape was born. The path for electrons stands upright like a thin plate, and the gate wraps around it on three sides. This is called a FinFET. Intel announced it in 2011 and first used it in mass production at its 22 nm generation.
An upright plate gives the gate more surface to control the current, without using more chip area seen from above. Other tricks in how parts are arranged and wired also squeezed the same circuit into less area. Overall density could rise without shrinking any single dimension to 0.7 times. Each company gave the next number to a generation once it judged these improvements were enough of a step forward.
What really shrinks: the spacing between parts
So what actually gets smaller as generations advance? What mostly decides a chip's density is how closely its parts are spaced. There are three main measures.
- Gate pitch: the distance from one gate to the next, side by side. The technical name is "contacted gate pitch"
- Metal pitch: the distance between the thinnest metal wires
- Cell height: the height of a basic building block of fixed shape used to assemble circuits (a standard cell). It depends on how many wires can run through it
The area of a cell is its height times its width. The width is set by how many gate pitches it spans. So the smaller the gate pitch and cell height, the more transistors fit in the same area.
Let's look at real numbers. For the 2 nm class, companies have not published these dimensions in detail. So we use a slightly older example that a manufacturer did publish. In 2017, Intel announced that its "10 nm" generation had a gate pitch of 54 nm and a tightest metal pitch of 36 nm. The name says 10 nm, but the main pitches are several tens of nanometers.
Now compare with atoms. 54 nm is about 230 times the spacing of silicon atoms (about 0.235 nm). From the name alone, chips seem to be getting close to atomic size. But the gates are still spaced more than 200 atoms apart.
Different companies, different "X nm"
Each company chooses its own generation names. So the same number can mean a different real density at a different company. In 2017, Intel engineer Mark Bohr pointed out that some companies advance the number even when density barely improves. He wrote that the names had stopped being a useful guide for comparing generations.
A clear example is Intel's own renaming. In July 2021, Intel renamed the generation it had called "10nm Enhanced SuperFin" to "Intel 7." It said the goal was to help the whole industry compare generations more accurately. It did not change any dimension. It changed only the name.
At the same time, Intel also dropped "nm" from its names. Its later generations are called "Intel 4," "Intel 3," "Intel 18A" and so on. The A stands for the angstrom, a unit of length (1 Å = 0.1 nm). So 18A means 18 Å, the same as 1.8 nm.
Companies also change the transistor's shape at different times. Samsung began using GAA, a shape explained below, at its "3 nm" generation in 2022. TSMC and Intel use it from their "2 nm class" generations, which entered mass production in 2025. Even generations with the same number are not the same inside.
A better yardstick: transistor density
To compare generations, transistor density is more useful than the name. It is the number of transistors that fit in 1 mm² (a 1 mm by 1 mm square). It is written in MTr/mm², where MTr means a million transistors. In 2017, Intel announced a density of 100.8 MTr/mm² for its 10 nm generation. That is about 100 million transistors per square millimeter.
Density figures need care, too. This value assumes two common types of building blocks, laid out in a fixed ratio. Real chips also have circuits that connect to the outside, and empty space. So the density of a whole chip is often lower than this figure. And there is no rule that makes companies count the same way.
Researchers have also proposed comparing several numbers side by side (IEEE Spectrum, 2020). The three numbers are the density of logic (computing circuits), the density of memory, and the density of the wiring that connects the two. The idea is that one number alone cannot capture how far the technology has come.
Transistors of the "2 nm class": GAA and nanosheets
In a FinFET, the gate surrounds the electron path on three sides. As sizes shrank further, three sides were no longer enough to hold back the current. So a shape in which the gate surrounds the path on all sides is coming into use. This is called GAA (gate-all-around).
The main type of GAA in use today stacks several thin silicon plates, each a few nanometers thick, with gaps between them. The gate wraps around each plate. These plates are called nanosheets. Changing the width of the sheets adjusts how much current can flow.
Here is what major companies have done (based on company announcements we could confirm as of October 2026).
| When | Event |
|---|---|
| May 2021 | IBM announces a "2 nm" prototype chip using nanosheets (gate length 12 nm) |
| June 2022 | Samsung announces it has started producing chips with GAA at its "3 nm" generation (calling it the world's first production with GAA) |
| July 2025 | Rapidus announces that it has confirmed the electrical characteristics of 2 nm GAA transistors prototyped at its fab in Chitose, Hokkaido |
| Late 2025 | Intel starts high-volume manufacturing of "Intel 18A," which uses GAA (Intel calls it RibbonFET), according to its annual report |
| October–December 2025 | TSMC starts volume production of "N2" (its 2 nm generation), its first process to use nanosheets, according to its website |
Production status and plans change often, so check each company's latest announcements.
Why shrink anyway, and the limits
Even though names and sizes no longer match, building finer features still matters a lot. The first reason is that more transistors fit in the same area. A chip of the same size can hold more computing circuits and memory.
The second is power. Smaller transistors and wires move less electric charge each time they switch on or off. For example, in 2022 TSMC announced that N2 was expected to cut power by 25–30% at the same speed as its previous 3 nm generation.
On the other hand, limits are in sight. A chip's fine patterns are drawn in a step that prints the circuit shape with light (exposure). The finest patterns need EUV lithography, which uses light with a wavelength of 13.5 nm. Its machines are very expensive. Each new generation also adds more process steps. So the cost of making each transistor no longer falls as much as it used to.
Heat is another problem. Until the mid-2000s, shrinking also allowed a lower supply voltage, so power per area did not rise. Today, the voltage is hard to lower. The more tightly parts are packed, the harder it becomes to remove the heat. So approaches other than shrinking, such as stacking chips, are also advancing. "Beyond Scaling" gives an overview of these directions.
Common misconceptions
Myth: "2 nm" means the transistor is 2 nm in size
In fact, it is a name that tells generations apart. Even IBM's "2 nm" prototype had a gate length of 12 nm. In Intel's "10 nm" generation, the gate pitch was 54 nm. The space one transistor takes up is far larger than 2 nm, both in length and in width. The myth arose because the number and the real size once roughly matched.
Myth: A smaller number always means a better chip
In fact, each company names its generations its own way, so numbers from different companies can't be compared. Chip performance also depends heavily on circuit design and on how much power the chip runs at. Chips that control cars and appliances, and sensors, are often made on older generations that are cheaper and proven. What matters is choosing the right generation for the job.
Myth: Chips will soon reach the size of one atom and stop shrinking
In fact, node names are not sizes, so names below 1 nm are possible. In 2024, TSMC announced "A16" (1.6 nm class) as its generation after 2 nm. Still, some parts are already very thin. In IBM's 2 nm prototype (2021), each nanosheet was about 5 nm thick. That is only about 20 times the spacing of silicon atoms. Making them much thinner is hard. So development is moving toward changing shapes, such as stacking parts vertically.
By the numbers
| Item | Length |
|---|---|
| Thickness of a human hair | 80,000–100,000 nm |
| Gate length in the "130 nm" generation (IEEE Spectrum, 2020) | 70 nm |
| Gate pitch in Intel's "10 nm" generation (announced 2017) | 54 nm |
| Tightest metal pitch in the same generation | 36 nm |
| Wavelength of the light used in EUV lithography | 13.5 nm |
| Gate length of IBM's "2 nm" prototype (2021) | 12 nm |
| How much a fingernail grows in one second (as described by the NNI) | about 1 nm |
| Distance between neighboring silicon atoms | about 0.235 nm |
In this table, the four gate lengths and pitches are real dimensions inside chips. In the "130 nm" generation, the gate length is smaller than the number in the name. In "10 nm" and "2 nm," the real dimensions are much larger than the name. There is no fixed relationship between the name and real dimensions.
Learn more
- See how transistor shapes changed, in tables: "Planar MOSFET vs. FinFET" and "FinFET vs. GAA."
- The step that draws fine patterns with light (lithography): with the lithography resolution calculator, try how the wavelength of light changes the narrowest line you can draw. "EUV vs. DUV lithography" compares EUV with the method before it.
- The roles of companies in the news: the glossary explains terms such as foundry, a company that manufactures chips for others.
- Beyond shrinking: "Beyond Scaling" covers 3D packaging, new materials and more in one place.
- To review the basics: "What Is a Semiconductor?" (the silicon crystal) and "What Is a Transistor?" (gate and channel, Moore's law).