Advanced transistors (FinFET and GAA)

In high-k/metal gate transistors, why is a very thin layer such as SiO2 often placed between the silicon and the high-k film (such as hafnium oxide)?

  1. ATo preserve the quality of the silicon interface and limit effects such as mobility degradation
  2. BTo increase the gate capacitance
  3. CTo lower the resistance of the metal gate
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Answer: A. To preserve the quality of the silicon interface and limit effects such as mobility degradation

Placing a high-k film directly on silicon tends to reduce channel mobility because of interface defects and charges and vibrations in the high-k film. An interfacial layer (IL) of SiO2 or similar, about 1 nm or less, is therefore inserted to maintain a good interface. Because the interfacial layer has a low permittivity, it must be kept as thin as possible to reduce EOT.

  • A. Correct. It is a layer for preserving interface quality.
  • B. The interfacial layer has low permittivity, so it actually lowers the gate capacitance.
  • C. It is unrelated to the gate electrode's resistance.
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More Advanced transistors (FinFET and GAA) questions

  1. Why have III-V compound semiconductors such as InGaAs been researched as future nMOS channel materials?
  2. Which correctly describes the transistor performance metric "Ion/Ioff ratio"?
  3. How did the subthreshold swing (SS) generally change with the move from planar transistors to FinFETs?
  4. As physical scaling becomes harder, what is the practice of considering design and process technology together to optimize area and performance called?
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