Planar MOSFET vs FinFET: Why the Industry Switched

A planar MOSFET has its gate on top of a flat channel, so the gate controls the channel from only one side. As gates became shorter than about 20 nm, the drain began to influence the channel too much, and leakage and short-channel effects grew. A FinFET raises the channel into a thin vertical fin and wraps the gate over three sides, which gives much tighter control. That is why logic moved from planar transistors to FinFETs starting at the 22 nm and 16/14 nm nodes.

AspectPlanar MOSFETFinFET
StructureThe gate lies on top of a flat channelThe gate wraps a thin vertical silicon fin on three sides
Gate controlFrom one side only: weaker at short gate lengthsFrom three sides: much stronger
Short-channel effects (such as DIBL)Severe at small dimensionsStrongly suppressed
Leakage currentHigher in scaled devicesLower
Subthreshold swingDegrades as the device shrinksClose to the ideal of about 60 mV per decade
Drive current per footprintLowerHigher: the channel width includes both fin sides and the top
Channel dopingHeavy, which causes random dopant fluctuationLight or undoped, so less variation
Width adjustmentContinuous: any width can be drawnIn steps: set by the number of fins
ManufacturingSimpler and cheaperMore complex: fin patterning and 3D gate formation
Where it is used todayMature nodes (28 nm and larger): analog, microcontrollers, RF, IoTAdvanced logic from 16/14 nm down to about 3 nm

Figures are typical orders of magnitude and vary by process generation and product.

When to use which

Planar
When cost matters more than the last bit of speed, and the design does not need the smallest nodes: analog, mixed-signal and many microcontrollers.
FinFET
When performance and low leakage at small dimensions are essential: smartphones, PCs and data-center processors.

FAQ

Why did planar transistors stop scaling?

Below a gate length of about 20 nm the drain began to influence the channel too much (short-channel effects such as DIBL), causing leakage that gate control from one side could not stop.

How does a FinFET reduce leakage?

The gate wraps three sides of a thin vertical fin, so it controls the channel better and the transistor turns off more completely.

Is planar technology obsolete?

No. Mature nodes at 28 nm and larger still use planar transistors for analog, microcontroller, RF and IoT chips, where cost matters more.

Why can FinFET channels be left undoped?

Strong gate control makes heavy channel doping unnecessary, which avoids random dopant fluctuation and reduces variation between transistors.

Check your understanding

Which describes a short-channel effect in MOSFETs?

  1. AShortening the gate makes the gate capacitance infinite
  2. BShortening the gate always doubles the channel mobility
  3. CShortening the gate lowers the threshold voltage and increases off-state leakage
Show answer and explanation

Answer: C. Shortening the gate lowers the threshold voltage and increases off-state leakage

As gate length shrinks, the source and drain depletion regions become relatively large and control part of the channel charge instead of the gate. Consequences include threshold roll-off, drain-induced barrier lowering (DIBL), degraded subthreshold swing and rising off-state leakage. Device characteristics also become highly sensitive to small process variations in gate length.

Which correctly describes DIBL (drain-induced barrier lowering)?

  1. AThe gate insulator breaks down over time
  2. BMetal atoms in wiring migrate due to current
  3. CThe higher the drain voltage, the lower the potential barrier at the source, lowering the threshold voltage
Show answer and explanation

Answer: C. The higher the drain voltage, the lower the potential barrier at the source, lowering the threshold voltage

With a short gate, the drain's field reaches toward the source and lowers the source-channel potential barrier. Threshold voltage therefore falls as drain voltage rises, increasing off-state leakage. DIBL is quoted as threshold shift per volt of drain bias (mV/V), kept to a few tens of mV/V or less in advanced transistors. In amplifiers it also lowers output resistance.

To adequately suppress short-channel effects in a FinFET, what is generally required of the fin width?

  1. AIt can be chosen independently of the gate length
  2. BMake it much wider than the gate length
  3. CMake it thinner than the gate length
Show answer and explanation

Answer: C. Make it thinner than the gate length

The thinner the fin, the better the gates on both sides reach its center, suppressing leakage through regions far from the gate. Fin width should be roughly half to equal the gate length or less, about 5–7 nm in advanced nodes. Making fins too thin, however, introduces threshold shifts from quantum confinement, mobility loss from surface scattering and process variability.

  1. How did the subthreshold swing (SS) generally change with the move from planar transistors to FinFETs?
  2. Which correctly describes the structure of a FinFET?
  3. Which correctly describes the "scale length (natural length) λ" used to estimate the severity of short-channel effects?

Practice Advanced transistors (FinFET and GAA) questions

Key terms explained

FinFET
A 3D transistor whose channel stands up like a fin and is surrounded by the gate on three sides. It suppresses short-channel effects well.
Short-channel effect
Phenomena in which, as gate length shrinks, the drain's electric field lowers the threshold voltage and increases off-state leakage current.
DIBL
Short for drain-induced barrier lowering. In short-channel MOSFETs, a higher drain voltage lowers the potential barrier at the source, reducing the threshold voltage and increasing off-state leakage.

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