Advanced transistors (FinFET and GAA)
In a CFET (complementary FET), which statement about connecting to the lower of the two stacked transistors is correct?
- AThe lower transistor has no gate, so only its source and drain need connections
- BBecause the upper transistor sits directly above it, front-side connections must be routed around the upper device, and connecting to the lower device directly from the backside is being studied
- CThe upper and lower transistors share all their sources and drains, so the lower device needs no separate connection
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Answer: B. Because the upper transistor sits directly above it, front-side connections must be routed around the upper device, and connecting to the lower device directly from the backside is being studied
A CFET (complementary FET) stacks nMOS and pMOS vertically to shrink cell area. The gates and output can be shared, but each source must connect to a different supply (VDD and VSS). Reaching the lower device from the front side requires deep contacts routed around the upper transistor, crowding wiring in a small cell. Connecting directly to the lower device from the wafer backside, combined with backside power delivery, is therefore being studied; at IEDM 2023 Intel reported a working CFET inverter with direct backside contacts to the lower device.
- A. The lower transistor also has a gate, often shared with the upper one.
- B. Correct. Access to the lower device becomes the wiring bottleneck.
- C. Even in an inverter, the nMOS and pMOS sources connect to different supplies.
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