FinFET vs GAA Transistors: Key Differences

In a FinFET the gate wraps a vertical fin of silicon on three sides. In a gate-all-around (GAA) transistor the gate surrounds the channel on all sides, usually as stacked horizontal nanosheets. Wrapping the channel more completely gives better control of leakage at short gate lengths, which is why leading chipmakers are moving from FinFET to GAA at the 3 nm and 2 nm class.

AspectFinFETGAA (nanosheet)
Gate structureThe gate covers three sides of a vertical finThe gate surrounds the channel on all four sides
Channel shapeA thin vertical fin of siliconHorizontal nanosheets (or nanowires), stacked on top of each other
Electrostatic controlGood, much better than planar transistorsEven better, which reduces leakage and supports shorter gates and lower supply voltage
Tuning the channel widthIn discrete steps: the width comes from the number of fins, because fin height is fixedFlexible: the sheet width and the number of sheets can be chosen per transistor
Main manufacturing stepsFin patterning (often with SADP or SAQP), fin isolation, gate formationEpitaxy of alternating Si and SiGe layers, selective removal of SiGe to release the sheets, inner spacers
Process complexityMature and well understoodMore complex, with new steps and tighter control
Self-heatingA concern, because heat escapes poorly from the thin channelA concern as well, since the sheets are surrounded by insulators
First volume productionIntel 22 nm (Tri-Gate), shipping in 2012First volume production at the 3 nm class, around 2022; other major makers followed
Vendor namesTri-Gate (Intel), FinFET (TSMC, Samsung and others)RibbonFET (Intel), MBCFET (Samsung), nanosheet (TSMC)

Figures are typical orders of magnitude and vary by process generation and product.

When to use which

FinFET
The workhorse of logic chips from about 22 nm to 5 nm and still used widely at 3 nm. It is mature, with well-known design rules and high yield.
GAA
The next step for the smallest nodes, where FinFETs struggle to control leakage and where designers want to tune the width of each transistor.
Beyond
Research continues on stacked complementary FETs (CFET), which place nMOS and pMOS on top of each other.

FAQ

Why is GAA better than FinFET?

In a gate-all-around transistor the gate surrounds the channel on all sides, which controls leakage better at very short gate lengths than a FinFET, where the gate covers three sides. It also lets designers tune the channel width of each transistor.

Are GAA transistors the same as nanosheet transistors?

Nanosheet transistors are the most common form of GAA: horizontal sheets stacked on top of each other and wrapped by the gate. Nanowire transistors are another GAA form. Intel calls its version RibbonFET and Samsung calls it MBCFET.

When did the industry move from FinFET to GAA?

FinFETs shipped in volume with Intel at 22 nm in 2012. GAA reached volume production at the 3 nm class around 2022, and other leading chipmakers followed.

What comes after GAA?

Research focuses on complementary FETs (CFET), which stack nMOS and pMOS transistors on top of each other to save area.

Check your understanding

Which correctly describes the structure of a FinFET?

  1. AThe gate wraps around a fin-shaped channel on three sides
  2. BA planar gate covers only the top of the channel
  3. CMetal contacts the channel directly with no gate insulator
Show answer and explanation

Answer: A. The gate wraps around a fin-shaped channel on three sides

A FinFET stands silicon up as a fin a few to over ten nm wide and tens of nm tall, with the gate wrapping both sidewalls and the top. Gate control from three sides suppresses short-channel effects better than planar devices, cutting off-state leakage, and the vertical dimension provides current-carrying width in a small footprint. It became the advanced-logic standard from the 22 nm generation.

Which correctly describes a GAA (gate-all-around) transistor?

  1. AThe gate covers only the top of the channel
  2. BThe gate surrounds the entire perimeter of the channel, such as nanosheets
  3. CIt has no gate and operates with only a source and drain
Show answer and explanation

Answer: B. The gate surrounds the entire perimeter of the channel, such as nanosheets

A gate-all-around (GAA) transistor stacks several channels shaped as sheets a few nm thick (nanosheets) or wires, each fully surrounded by the gate. Control from all sides is even stronger than in a FinFET, suppressing short-channel effects down to shorter gate lengths. Samsung adopted it at 3 nm (2022), TSMC at 2 nm and Intel at 18A, making it the successor standard to the FinFET.

How is the effective channel width of a FinFET adjusted?

  1. ABy changing the number of fins, so the width takes discrete values
  2. BBy changing the gate voltage
  3. CIt can be set to any continuous value, as in planar transistors
Show answer and explanation

Answer: A. By changing the number of fins, so the width takes discrete values

In a FinFET, fin height and width are fixed by the process, so channel width is adjusted only by the number of fins—a discrete quantity ("width quantization"). This makes it hard to set fine current ratios in analog circuits or tune the strength ratios among SRAM cell transistors, constraining design. Nanosheet GAA devices relax this limitation.

  1. Compared with FinFETs, what is a design advantage of nanosheet GAA transistors?
  2. In manufacturing nanosheet GAA transistors, why is only the SiGe selectively removed from stacked alternating Si and SiGe layers?
  3. Which company and generation first put FinFETs (called Tri-Gate by Intel) into volume-production logic products?

Practice Advanced transistors (FinFET and GAA) questions

Key terms explained

FinFET
A 3D transistor whose channel stands up like a fin and is surrounded by the gate on three sides. It suppresses short-channel effects well.
GAA (gate-all-around)
A transistor structure in which the gate surrounds the channel on all sides. It controls current better than FinFET and is used in the generations after FinFET.
Nanosheet
A GAA transistor structure that stacks several thin, plate-like silicon channels vertically, each surrounded by the gate. Current can be tuned by the sheet width.

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