What Is a GAA Transistor? Gate-All-Around Nanosheets
A GAA transistor is a transistor whose "gate," the part that turns it on and off, wraps all the way around the path for electrons. This makes it easier to stop current leaking while the transistor is off, even when it is very small. Today, a version made of stacked thin plates a few nm thick (nanosheets) is coming into use. It appears in leading-edge chips, such as the "2 nm class."
What you'll learn
- Why transistors get harder to switch fully off as they shrink
- How the gate's coverage of the channel grew: planar → FinFET → GAA
- How stacked nanosheets carry current, and why choosing their width helps
- How GAA is made (in outline), when companies started using it, and what may follow: CFET
Prerequisites: it helps to know that a transistor is a switch that turns on and off when a voltage is applied to its gate. "What Is a Transistor?" explains this.
In everyday life: "GAA" in the news
"Samsung begins 3 nm chip production with GAA." "TSMC starts volume production at 2 nm." Since around 2022, the term GAA has appeared in news like this. In October 2025, Intel also unveiled a new chip for laptops, code-named Panther Lake. It is made with a technology called "Intel 18A," which uses GAA.
News stories often mention "2 nm" and "GAA" together, but they are two separate things. "2 nm" is the name of a generation of chipmaking technology. It does not mean that any part is 2 nm long (see "What Does 2nm or 3nm Mean?"). GAA, on the other hand, is the name of a transistor shape.
This article starts with why transistors needed a new shape. Then it looks at what GAA looks like, how it is made, and what may come next.
A transistor must switch off reliably
First, a quick review. The transistors inside a chip are tiny switches flipped by electricity. Electrons enter at the source and leave at the drain, with a path for them in between. The gate sits above this path. A voltage on the gate opens the path and turns the switch on. Lowering the voltage turns it off.
When the switch is off, something like a "wall" between the source and drain blocks the electrons. The gate uses its voltage to raise or lower this wall, which stops or allows the flow. It is not a real wall. It is a difference in energy levels for the electrons, and calling it a wall makes it easier to picture.
An ideal switch lets no current through at all when it is off. Real transistors leak a little current even when off. The leak from one transistor is tiny, but a chip holds billions of them. Added together, the leaks drain the battery and make heat even while the chip is idle (see "What Is CMOS?").
Shrink it, and the gate can no longer guard the wall
Making a transistor smaller also shortens the distance between source and drain. The drain voltage then reaches deep into the path. It pushes the wall down, no matter what the gate is doing. Engineers call this DIBL, short for "drain-induced barrier lowering" (the barrier is the wall).
As a result, current leaks even when the gate is set to off, because the wall is lower. The voltage where the transistor flips between on and off also shifts a lot if the path length differs only slightly. Engineers call the path for electrons the channel. These problems of a short channel are grouped together as the short-channel effect.
The idea behind the fix is simple. Make the gate touch the channel more closely and over more area, so it controls the wall more strongly than the drain does. Making the channel thinner works the same way, because the gate's influence then reaches all the way through. The history of transistor shapes is a story of covering more sides with the gate.
When the channel gets even shorter, down to a few nm, electrons also start to slip through the wall. This is a separate limit, and a cleverer shape can hardly prevent it. "Quantum Tunneling in Transistors and Flash Memory" explains it.
Planar → FinFET → GAA: more sides covered
The flat shape, called planar, was used for a long time. In it, the gate touched only one side of the channel: the top. The lower part of the channel was far from the gate and easily affected by the drain.
The next shape stands the channel upright like a thin plate. The gate then covers it on three sides: the top and both sides. The upright plate looks like a fish's fin, so this is called a FinFET. In 2011, Intel announced it would use this shape in mass production, starting with its 22 nm chips (Intel calls it Tri-Gate).
As shrinking went on, even three sides were no longer enough. The base of a FinFET fin is attached to the silicon underneath, and the gate cannot wrap around that part. So engineers lifted the channel off the base and wrapped the gate all the way around it. This is GAA, short for gate-all-around: the gate is on every side.
Comparison pages set out the differences among the three shapes in tables: "Planar MOSFET vs FinFET" and "FinFET vs GAA Transistors."
Nanosheets: stacking thin plates for more current
A thinner channel lets the gate's influence reach all the way through. But a single thin channel can carry only a small current. With little current, the circuits it drives cannot run fast.
So GAA stacks several thin plates of silicon, with gaps between them. The gate wraps each plate, and every plate connects to the same source and drain. When the transistor turns on, current flows through all the plates at once. Their total is the transistor's current. These thin plates are called nanosheets.
Let's look at an example of the sizes. In 2021, IBM announced a "2 nm" prototype. According to reports that read IBM's images, the sheets were stacked three high, and each was about 5 nm thick. That is only about 20 times the spacing between silicon atoms (about 0.235 nm).
Each company uses its own name. Samsung named its version MBCFET (a transistor with several bridge-like channels). Intel calls it RibbonFET (a transistor with ribbon-shaped channels), and TSMC calls it "nanosheet." The details of how they are made differ. But the basic idea is the same: stack plates and wrap the gate around them.
Choosing the channel width is another benefit
Some parts of a circuit need a large current to run fast. Other parts should use less current to save power. So it helps if each transistor can have its own channel width.
In a FinFET, all the fins on a chip are made with the same height and thickness. To get more current, you place two or three fins side by side. So current can only be chosen in steps: one fin's worth, two fins' worth, and so on.
With nanosheets, designers can choose the sheet width when they draw the circuit layout. Circuits where speed matters can use wide sheets. Circuits that must save power or area can use narrow ones. In its 2022 announcement, Samsung also named this as a benefit: changing the sheet width can tune power and performance. In practice, though, the width can only be chosen within the manufacturing rules.
How is it made? Stack two layers, then remove one
Many plates must float in the air, and the gate must fill even the gaps between them. How is that done? The basic idea is to build a sandwich of two kinds of layers, one after the other, and later remove only one kind. Here we cover only the outline and skip many of the steps.
One material is silicon. The other is SiGe (silicon-germanium), a crystal made by mixing the element germanium into silicon. Its atomic spacing is close to that of silicon, so thin layers stack neatly. Yet the two wear away at different rates, so one can be removed later while the other stays.
First, SiGe and silicon layers a few nm thick are stacked in turn. They go on a round silicon plate (a wafer), which is the base for the chips. Each layer is grown so it continues the atomic pattern of the crystal below. This method is called epitaxial growth. Next, the stack is cut into narrow strips, and the source and drain are built at both ends. Patterns are drawn with light (lithography), and material is carved away by etching.
Now only the SiGe is removed. This uses etching under conditions that remove SiGe quickly but barely touch silicon. How large this difference is gets called the selectivity. Once the SiGe is gone, the silicon plates remain like bridges, held up by the source and drain at both ends.
Finally, a very thin insulating film and the gate metal go into the gaps around the plates. The gaps are very narrow, so the film is built one atomic layer at a time, a method called ALD (see "What Is Thin-Film Deposition?"). In practice, more steps are needed. For example, insulating spacers go at the ends of the gaps so the gate does not touch the source and drain.
Stacking two kinds of layers, removing only one of them, and filling the gaps between the plates with the gate: none of these steps existed for FinFETs. More steps and harder ones also make the chips more costly to make. "How Are Chips Made?" explains the whole chipmaking flow.
Who uses it, and since when?
Based on each company's official announcements, here is when GAA came into use, in time order (as could be confirmed in October 2026). The order shows timing only. It does not rank the technologies.
| When | What each company announced |
|---|---|
| June 2022 | Samsung announced it had started initial production of its "3 nm" generation using GAA (MBCFET) at its plant in Hwaseong, South Korea |
| July 2025 | Rapidus announced it had confirmed the electrical characteristics of 2 nm GAA transistors prototyped at its plant in Chitose, Hokkaido, Japan. It said it aims to start mass production in 2027 |
| Late 2025 | Intel began high-volume manufacturing of "Intel 18A," which uses GAA (RibbonFET), according to its annual report for fiscal 2025. 18A also uses backside power delivery (PowerVia), which moves the power wiring to the back of the wafer |
| October–December 2025 | TSMC began volume production of "N2" (its 2 nm generation), which TSMC calls its "first-generation nanosheet" technology (according to its website) |
Within the same "3 nm" generation, Samsung used GAA while TSMC used FinFETs (TSMC's 2022 announcement). Generation names and transistor shapes do not match one to one. Production status and plans change often, so check each company's own announcements for the latest information.
What comes after GAA? CFET stacks nMOS on pMOS
Most chip circuits combine two kinds of transistors that act in opposite ways: nMOS and pMOS (see "What Is CMOS?"). Today, the two sit side by side on the chip. Stacking one on top of the other would let the same circuit fit in less area. This shape is called CFET (complementary FET).
CFET is still at the research and development stage. In December 2023, at the international conference IEDM, Intel, Samsung and TSMC each presented CFET research. IEEE, a society of electrical and electronics engineers, covered all three in its magazine. In June 2024, imec, a research institute in Belgium, also announced a prototype of stacked transistors that worked with their contacts connected.
In a December 2024 announcement, imec set out its own technology outlook. In it, imec plans to use CFET from a generation it calls "A7." The "A" stands for the angstrom, a unit of length (0.1 nm), so A7 is a name that corresponds to 0.7 nm. But this, too, is a generation name, not a dimension. For the generation before that, imec is considering a shape called a "forksheet." It brings nMOS and pMOS sheets close together, with a thin wall between them.
Common misconceptions
Myth: With GAA, there is no leakage when the transistor is off
In fact, GAA only reduces leakage. Even when the gate fully surrounds the channel, some electrons still get over the wall with heat energy. Electrons can also slip through the gate's thin insulating film. That is why today's chips still use other tricks, such as cutting power to parts that are not in use. The myth comes from how absolute the phrase "all around" sounds.
Myth: "2 nm" is the thickness of a GAA sheet or the length of its gate
In fact, it is a name that tells generations apart. Even in IBM's "2 nm" prototype, the sheets were about 5 nm thick and the gate was about 12 nm long. Also, Samsung began using GAA at "3 nm," while TSMC uses it from "2 nm." Generations with the same number can use different shapes, so the number does not describe the transistor's shape either.
Myth: Now that GAA is here, FinFET and planar transistors are no longer used
In fact, the switch has happened only in some leading-edge generations. Generations that use FinFETs, such as TSMC's 3 nm generation, are still in mass production. Chips for cars and home appliances often use older, cheaper generations or planar transistors. New shapes need more steps and cost more, so they are used first where they are really needed.
By the numbers
| Item | Number |
|---|---|
| Sides of the channel the gate touches | Planar: 1; FinFET: 3; GAA: all around |
| Sheet thickness in IBM's "2 nm" prototype (2021, as reported) | About 5 nm |
| Number of sheets in the same prototype | 3 |
| Gate length in the same prototype (as IBM described it) | About 12 nm |
| Spacing between silicon atoms | About 0.235 nm |
| TSMC N2 power use (2022 projection, compared with N3, the 3 nm generation, at the same speed) | 25–30% lower |
So plates only about 20 times the atomic spacing thick are stacked, held up in the air and wrapped by the gate. Even so, both the sheet thickness and the gate length are larger than the "2 nm" in the name. There is no fixed relationship between the number in the name and real dimensions.
The TSMC figure is a projection the company gave in 2022, and the comparison is with the previous 3 nm generation (N3). It is the effect of the whole generation, including wiring and circuit improvements, not of the transistor shape alone.
Learn more
- Another approach: FD-SOI also curbs leakage by making the channel a thin layer. "SOI vs Bulk Silicon" compares the options.
- Try the numbers: the MOSFET I-V curves tool shows how gate voltage relates to the current that flows. The figure "nMOS channel" shows how the channel forms.
- Ideas beyond shrinking: "Beyond Scaling" brings together CFET, backside power delivery and chip stacking.
- The industry: "What Is a Semiconductor Foundry?" explains companies that make chips for others. "What Is Moore's Law?" covers the history of shrinking.