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Timing analysis and CDC

To fix a hold violation, delay buffers are inserted in the data path. What is the most important thing to check when doing this?

  1. AThat the same amount of delay is also added to the capturing flip-flop's clock to keep the skew at zero
  2. BThat the added delay does not leave the same path short of setup slack
  3. CThat high-drive buffers are inserted to keep the delay as small as possible
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Answer: B. That the added delay does not leave the same path short of setup slack

A hold violation means the data arrives too early, so delay is added to the data path to make it arrive later. However, the added delay also delays the arrival time for setup. A buffer that improves hold by 0.05 ns at the fast corner can add 0.1 ns or more of delay at the slow corner, so buffers must be inserted only within the available setup margin. Adding the same delay to the capture clock cancels out the improvement, and raising the drive strength to reduce delay defeats the purpose.

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More Timing analysis and CDC questions

  1. On a path with a clock period of 1.25 ns (800 MHz), the clock-to-output delay plus combinational logic delay totals 1.05 ns, the setup time is 0.05 ns, and the setup clock uncertainty is set to 0.05 ns. What is the setup slack?
  2. In clock uncertainty settings, period jitter is often included for setup but not for hold. Why?
  3. In STA, which combination correctly gives the corner conditions mainly used to check setup and hold?
  4. For OCV derating in setup analysis, the launch clock path and data path delays are multiplied by 1.1 and the capture clock path delay by 0.9. With a launch clock path of 1.0 ns, a data path (including clock-to-output) of 1.5 ns, a capture clock path of 1.0 ns (no common portion), a period of 3.0 ns and a setup time of 0.1 ns, what is the setup slack?
  5. In STA with OCV derating, when the launch and capture clock paths share a common portion, which correctly describes CRPR (common path pessimism removal)?