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Timing analysis and CDC

Which is the correct structure of a reset synchronizer that generates, from an active-low external reset, an internal reset that is "asserted asynchronously and deasserted synchronously"?

  1. AConnect the external reset to the asynchronous reset pins of two flip-flops, tie the first stage's D input to 1, and use the second stage's output as the internal reset
  2. BSynchronize the external reset by feeding it into the D inputs of two flip-flops, and use only that output as the internal reset
  3. CUse the AND of the external reset and the clock directly as the internal reset
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Answer: A. Connect the external reset to the asynchronous reset pins of two flip-flops, tie the first stage's D input to 1, and use the second stage's output as the internal reset

When the external reset goes to 0, the two flip-flops are immediately cleared to 0 through their asynchronous reset pins without waiting for the clock, and the internal reset is asserted. After the external reset returns to 1, the 1 on the first stage's D input shifts one stage per clock, and on the second clock the second stage's output becomes 1, releasing reset. The release is aligned to the clock, and even if the first stage goes metastable, one period is secured for it to resolve before it reaches the second stage. Synchronizing only through the D input does not apply reset while the clock is stopped.

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