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Timing analysis and CDC

For OCV derating in setup analysis, the launch clock path and data path delays are multiplied by 1.1 and the capture clock path delay by 0.9. With a launch clock path of 1.0 ns, a data path (including clock-to-output) of 1.5 ns, a capture clock path of 1.0 ns (no common portion), a period of 3.0 ns and a setup time of 0.1 ns, what is the setup slack?

  1. A1.05 ns
  2. B1.40 ns
  3. C1.25 ns
Show answer and explanation

Answer: A. 1.05 ns

OCV derating accounts for delay varying with location even within the same chip, and for setup assumes the most pessimistic combination (slow launch side, early capture clock). The arrival time is 1.1 × (1.0 + 1.5) = 2.75 ns and the required time is 3.0 + 0.9 × 1.0 − 0.1 = 3.8 ns, so the slack is 1.05 ns. 1.40 ns is the value without derating, and 1.25 ns applies the factor to the data path only. In hold analysis the factors are applied the other way around.

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More Timing analysis and CDC questions

  1. In STA with OCV derating, when the launch and capture clock paths share a common portion, which correctly describes CRPR (common path pessimism removal)?
  2. In a circuit running on a 2.0 ns clock, a path has a data arrival time (clock-to-output plus combinational logic delay) of 3.3 ns and a setup time of 0.1 ns. Since this path only needs to capture once every two cycles, a setup multicycle path of 2 is set. What is the setup slack?
  3. When a setup multicycle path of N (N ≥ 2) is set, a hold multicycle path of N − 1 is normally set as well. Why?
  4. For which path is it appropriate to set a false path (set_false_path)?
  5. With a 2.0 ns clock at 50% duty cycle, a path launches on the rising edge and captures on the falling edge. With a setup time of 0.1 ns and zero skew, what is the maximum allowed sum of the clock-to-output delay and combinational logic delay?