English
Menu

Timing analysis and CDC

In a circuit running on a 2.0 ns clock, a path has a data arrival time (clock-to-output plus combinational logic delay) of 3.3 ns and a setup time of 0.1 ns. Since this path only needs to capture once every two cycles, a setup multicycle path of 2 is set. What is the setup slack?

  1. A−1.4 ns
  2. B+2.6 ns
  3. C+0.6 ns
Show answer and explanation

Answer: C. +0.6 ns

A multicycle path of 2 moves the capturing edge from one period later to two periods later. The required time is 2 × 2.0 − 0.1 = 3.9 ns and the arrival time is 3.3 ns, so the slack is +0.6 ns. −1.4 ns is calculated with the normal single cycle, and +2.6 ns allows three cycles' worth of time. A multicycle path must be set only after the designer has confirmed that the circuit actually captures only every two cycles, for example via an enable signal.

Practice this topic Back to topic

Books on Timing analysis and CDC Ad

As an Amazon Associate I earn from qualifying purchases.

More Timing analysis and CDC questions

  1. When a setup multicycle path of N (N ≥ 2) is set, a hold multicycle path of N − 1 is normally set as well. Why?
  2. For which path is it appropriate to set a false path (set_false_path)?
  3. With a 2.0 ns clock at 50% duty cycle, a path launches on the rising edge and captures on the falling edge. With a setup time of 0.1 ns and zero skew, what is the maximum allowed sum of the clock-to-output delay and combinational logic delay?
  4. With a 2.0 ns clock, a path runs from a flip-flop that launches data on the rising edge at time 0 to a latch that opens (becomes transparent) at 1.0 ns and closes at 2.0 ns. If the data arrives at the latch at 1.4 ns, how much time has been borrowed at this latch (time borrowing)?
  5. In a circuit that stops the clock with a two-input AND gate of the clock and an enable signal, what does the STA clock gating check verify?