Timing analysis and CDC

A hold violation (slack −0.03 ns) is found on an ordinary path that launches and captures on the rising edge of the same clock. How is this violation affected if the clock frequency is halved?

  1. AThe hold check does not depend on the clock period, so the violation remains
  2. BThe period doubles, so the violation is resolved
  3. CThe longer period makes the violation even larger
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Answer: A. The hold check does not depend on the clock period, so the violation remains

The hold check looks at whether new data launched by the same clock edge corrupts the previous data at the capturing side, and on such paths the clock period does not appear in the equation. Lowering the frequency therefore leaves the −0.03 ns slack unchanged, without making it worse either. Setup, by contrast, depends on the period, so lowering the frequency can rescue it. A hold violation found after manufacturing tends to be a fatal defect that cannot be fixed by adjusting the frequency, so it is important to fix it reliably at the design stage.

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More Timing analysis and CDC questions

  1. To fix a hold violation, delay buffers are inserted in the data path. What is the most important thing to check when doing this?
  2. On a path with a clock period of 1.25 ns (800 MHz), the clock-to-output delay plus combinational logic delay totals 1.05 ns, the setup time is 0.05 ns, and the setup clock uncertainty is set to 0.05 ns. What is the setup slack?
  3. In clock uncertainty settings, period jitter is often included for setup but not for hold. Why?
  4. In STA, which combination correctly gives the corner conditions mainly used to check setup and hold?
  5. For OCV derating in setup analysis, the launch clock path and data path delays are multiplied by 1.1 and the capture clock path delay by 0.9. With a launch clock path of 1.0 ns, a data path (including clock-to-output) of 1.5 ns, a capture clock path of 1.0 ns (no common portion), a period of 3.0 ns and a setup time of 0.1 ns, what is the setup slack?