Timing analysis and CDC

How does the mean time between failures (MTBF) due to metastability change when a two-flip-flop synchronizer is extended to three stages?

  1. AThe time available for metastability to resolve increases by about one period, and MTBF grows exponentially
  2. BMTBF increases 1.5 times, in proportion to the number of stages
  3. CHow likely metastability is depends on the input side, so MTBF does not change
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Answer: A. The time available for metastability to resolve increases by about one period, and MTBF grows exponentially

Synchronizer MTBF is approximately MTBF = e^(t_r/τ) ÷ (T_0 × f_clk × f_data), where t_r is the time available for metastability to resolve and τ and T_0 are constants determined by the flip-flop's characteristics. Adding a stage extends t_r by about one period. For example, with τ = 20 ps, increasing t_r by 1 ns multiplies MTBF by e^50, more than 10^21 times. The probability of the first stage going metastable is unchanged, but the probability that it resolves before propagating further rises sharply.

Two-flip-flop synchronizer Source clock domain Destination clock domain Source FF FF1 FF2 Async Direct Synced output Source clock Dest. clock Metastable risk Dest. clock FF1 output Unsettled FF2 output ~1 cycle If FF1 settles before the next edge, FF2 gets the correct value
Two-flip-flop synchronizer · View in diagrams
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More Timing analysis and CDC questions

  1. Raising the clock frequency on the receiving side of a synchronizer shortens MTBF. Why?
  2. Which is a correct precaution about the connection between the first and second stages of a two-flip-flop synchronizer?
  3. Why must the output of combinational logic in the sending clock domain not be fed directly into a synchronizer in the receiving domain?
  4. Each bit of 4-bit data is passed to another clock domain through its own two-stage synchronizer. What problem can occur when the data changes from 0111 to 1000?
  5. Which is a correct way to pass multi-bit data safely to another clock domain?