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Timing analysis and CDC

Each bit of 4-bit data is passed to another clock domain through its own two-stage synchronizer. What problem can occur when the data changes from 0111 to 1000?

  1. AThe bits may be captured in different cycles, so an intermediate value such as 1111 or 0000 may be received
  2. BPassing through the synchronizers aligns all bits to the same cycle, so no problem occurs
  3. CAll four bits become metastable and never return to either 0 or 1
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Answer: A. The bits may be captured in different cycles, so an intermediate value such as 1111 or 0000 may be received

For each bit, a two-stage synchronizer does not determine whether a change is captured at the current edge or the next one. In a change from 0111 to 1000 all four bits change, so for one cycle the receiver may get a value in which only some bits have their new value, such as 1111, 0000 or 0100. If the receiver uses that value, it malfunctions. Metastability resolves to 0 or 1 over time. For counter values, convert to Gray code so that only one bit changes; for arbitrary data, use a handshake or an asynchronous FIFO.

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More Timing analysis and CDC questions

  1. Which is a correct way to pass multi-bit data safely to another clock domain?
  2. A pulse that is 1 for only one cycle (2 ns) in a 500 MHz clock domain is passed to a 100 MHz domain through a two-stage synchronizer. What problem can occur?
  3. To pass a level signal reliably from a 400 MHz domain to a 100 MHz domain through a synchronizer, the signal width should be at least 1.5 times the receiving clock period. What is the minimum width in sending-clock cycles?
  4. In toggle synchronization (a scheme in which the sending side generates and passes a level signal that inverts each time a pulse arrives), how is the original pulse recovered on the receiving side?
  5. What constraint applies when passing pulses from a fast clock domain to a slow one with toggle synchronization?