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Timing analysis and CDC

Which is a drawback of transferring data between clock domains with a handshake?

  1. ASynchronization of req and ack makes a round trip, so each transfer takes many cycles, making it unsuited to continuous high-volume transfer
  2. BPassing multi-bit data corrupts it through misalignment of per-bit synchronization
  3. CIt can only be used when the sending and receiving clocks have the same frequency
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Answer: A. Synchronization of req and ack makes a round trip, so each transfer takes many cycles, making it unsuited to continuous high-volume transfer

In a four-phase handshake, req takes two synchronization cycles to reach the receiver and ack two cycles to return to the sender, and returning each to 0 takes the same again, so one transfer takes 8 or more cycles in total across both domains. It therefore suits data passed occasionally, such as control register settings. The data stays stable throughout the transfer, so errors from bit misalignment do not occur, and any frequency ratio works. For streaming data almost every cycle, use an asynchronous FIFO.

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More Timing analysis and CDC questions

  1. Why are the write and read pointers of an asynchronous FIFO converted to Gray code before being synchronized into the other domain?
  2. What is the 4-bit binary value 0110 (decimal 6) converted to Gray code?
  3. In a 16-word-deep asynchronous FIFO, why are the write and read pointers made 5 bits, one bit more than the address?
  4. In a 16-word-deep asynchronous FIFO with 5-bit Gray code pointers, what is the correct condition for detecting full on the write side?
  5. In an asynchronous FIFO, the other side's pointer is used after synchronization, so the pointer value seen is 2–3 cycles stale. What effect does this delay have on full/empty detection?