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Timing analysis and CDC

Why must the output of combinational logic in the sending clock domain not be fed directly into a synchronizer in the receiving domain?

  1. ABecause the receiving side may capture a momentary glitch on the combinational output as a valid value
  2. BBecause combinational outputs have a low voltage and the receiving flip-flop does not respond
  3. CBecause capturing a combinational output always causes metastability
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Answer: A. Because the receiving side may capture a momentary glitch on the combinational output as a valid value

Within the same clock domain, glitches settle before the next clock edge and cause no problem. When captured by an asynchronous clock, however, the edge can come at any time, so a momentary 1 pulse on a signal that should be 0 can be captured. The rule is therefore that signals crossing domains come directly from a flip-flop output in the sending domain. Metastability does not occur every time, and CDC verification tools also flag combinational logic in front of synchronizers.

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More Timing analysis and CDC questions

  1. Each bit of 4-bit data is passed to another clock domain through its own two-stage synchronizer. What problem can occur when the data changes from 0111 to 1000?
  2. Which is a correct way to pass multi-bit data safely to another clock domain?
  3. A pulse that is 1 for only one cycle (2 ns) in a 500 MHz clock domain is passed to a 100 MHz domain through a two-stage synchronizer. What problem can occur?
  4. To pass a level signal reliably from a 400 MHz domain to a 100 MHz domain through a synchronizer, the signal width should be at least 1.5 times the receiving clock period. What is the minimum width in sending-clock cycles?
  5. In toggle synchronization (a scheme in which the sending side generates and passes a level signal that inverts each time a pulse arrives), how is the original pulse recovered on the receiving side?