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Timing analysis and CDC

With a 2.5 ns (400 MHz) clock, set_output_delay 0.8 ns is set on an output port. If the clock-to-output delay of the flip-flop driving the port is 0.2 ns, what is the maximum delay allowed for the combinational logic and wiring from the flip-flop to the output port (ignore clock latency)?

  1. A1.5 ns
  2. B2.3 ns
  3. C1.7 ns
Show answer and explanation

Answer: A. 1.5 ns

The 0.8 ns output delay is time used outside the chip, so 2.5 − 0.8 = 1.7 ns is available on chip. Subtracting the flip-flop's 0.2 ns clock-to-output delay leaves 1.5 ns for the combinational logic and wiring. 2.3 ns is calculated without the output delay, and 1.7 ns forgets to subtract the clock-to-output delay. Placing a flip-flop right before the output port so that the output comes directly from a register keeps the internal delay small and stable, making the constraint easier to meet.

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