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Timing analysis and CDC

When the clock arrives at the capturing flip-flop later than at the launching flip-flop (positive skew), what is the effect on setup and hold?

  1. ASetup gains margin and hold becomes tighter
  2. BSetup becomes tighter and hold gains margin
  3. CNeither is affected, because the clock period does not change
Show answer and explanation

Answer: A. Setup gains margin and hold becomes tighter

Setup concerns capture at the next edge, so the later the capture edge, the longer the data arrival can be waited for. Hold checks that new data launched by the same edge does not overwrite the previous data, so the later the capture edge, the greater the risk that the new data arrives too early. For example, with a skew of +0.1 ns, setup slack increases by 0.1 ns and hold slack decreases by 0.1 ns. Negative skew has the opposite effect.

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More Timing analysis and CDC questions

  1. The launching flip-flop's minimum clock-to-output delay is 0.08 ns, the minimum combinational logic delay is 0.02 ns and the capturing flip-flop's hold time is 0.05 ns. If the clock arrives at the capturing flip-flop 0.1 ns later than at the launching flip-flop, what is the hold slack?
  2. A hold violation (slack −0.03 ns) is found on an ordinary path that launches and captures on the rising edge of the same clock. How is this violation affected if the clock frequency is halved?
  3. To fix a hold violation, delay buffers are inserted in the data path. What is the most important thing to check when doing this?
  4. On a path with a clock period of 1.25 ns (800 MHz), the clock-to-output delay plus combinational logic delay totals 1.05 ns, the setup time is 0.05 ns, and the setup clock uncertainty is set to 0.05 ns. What is the setup slack?
  5. In clock uncertainty settings, period jitter is often included for setup but not for hold. Why?