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Timing analysis and CDC

In STA with OCV derating, when the launch and capture clock paths share a common portion, which correctly describes CRPR (common path pessimism removal)?

  1. AIt treats the delay of the common portion as zero and recalculates the clock arrival times
  2. BIt removes the impossible extra pessimism caused by applying separate slow and fast values to the common portion
  3. CIt applies an even larger derating factor to the common portion to stay on the safe side
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Answer: B. It removes the impossible extra pessimism caused by applying separate slow and fast values to the common portion

OCV estimates the launch clock path as slow and the capture clock path as fast, but the common portion from the root to the branch point is physically the same buffers and wires, so it cannot be both slow and fast within a single edge. If the common portion has a delay of 1.0 ns and the factors are 1.1 and 0.9, the 0.2 ns difference between 1.1 ns and 0.9 ns is extra pessimism. CRPR adds this difference back to the slack, bringing the result closer to reality. It does not set the common delay to zero, and enlarging the factor is the opposite operation.

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More Timing analysis and CDC questions

  1. In a circuit running on a 2.0 ns clock, a path has a data arrival time (clock-to-output plus combinational logic delay) of 3.3 ns and a setup time of 0.1 ns. Since this path only needs to capture once every two cycles, a setup multicycle path of 2 is set. What is the setup slack?
  2. When a setup multicycle path of N (N ≥ 2) is set, a hold multicycle path of N − 1 is normally set as well. Why?
  3. For which path is it appropriate to set a false path (set_false_path)?
  4. With a 2.0 ns clock at 50% duty cycle, a path launches on the rising edge and captures on the falling edge. With a setup time of 0.1 ns and zero skew, what is the maximum allowed sum of the clock-to-output delay and combinational logic delay?
  5. With a 2.0 ns clock, a path runs from a flip-flop that launches data on the rising edge at time 0 to a latch that opens (becomes transparent) at 1.0 ns and closes at 2.0 ns. If the data arrives at the latch at 1.4 ns, how much time has been borrowed at this latch (time borrowing)?