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Timing analysis and CDC

A pulse that is 1 for only one cycle (2 ns) in a 500 MHz clock domain is passed to a 100 MHz domain through a two-stage synchronizer. What problem can occur?

  1. AThe pulse is stretched to five cycles on the receiving side
  2. BThe pulse is always captured twice and treated as two events
  3. CThe pulse can fall between edges of the receiving clock and be lost without being captured
Show answer and explanation

Answer: C. The pulse can fall between edges of the receiving clock and be lost without being captured

The 100 MHz receiving clock has an edge only every 10 ns, so a 2 ns pulse often starts and ends between edges, in which case it is not captured at all. A synchronizer only reduces the probability of malfunction due to metastability; it does not catch short pulses, nor does it stretch them according to the frequency ratio. When passing a pulse from a fast domain to a slow one, stretch the pulse to well beyond the receiving period, or use toggle synchronization or a handshake.

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More Timing analysis and CDC questions

  1. To pass a level signal reliably from a 400 MHz domain to a 100 MHz domain through a synchronizer, the signal width should be at least 1.5 times the receiving clock period. What is the minimum width in sending-clock cycles?
  2. In toggle synchronization (a scheme in which the sending side generates and passes a level signal that inverts each time a pulse arrives), how is the original pulse recovered on the receiving side?
  3. What constraint applies when passing pulses from a fast clock domain to a slow one with toggle synchronization?
  4. In a four-phase handshake using req and ack, what is the correct signal sequence for passing one data item?
  5. Which is a drawback of transferring data between clock domains with a handshake?