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Timing analysis and CDC

In a 16-word-deep asynchronous FIFO, why are the write and read pointers made 5 bits, one bit more than the address?

  1. ABecause 5 bits are needed to represent the addresses of 16 words
  2. BSo that when the pointers match, empty (same lap) can be distinguished from full (one lap apart)
  3. CTo use the extra bit as parity for detecting pointer errors
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Answer: B. So that when the pointers match, empty (same lap) can be distinguished from full (one lap apart)

The addresses of 16 words fit in 4 bits, but with 4-bit pointers alone, when the read and write addresses match it is impossible to tell whether the FIFO is empty because everything has been read, or full because writing has gone a full lap and caught up. Adding a fifth bit that indicates the lap means that, comparing in binary, the FIFO is empty when all 5 bits match and full when only the MSB differs. With Gray code pointers, the comparison for full is slightly different. The bit is not used as parity.

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More Timing analysis and CDC questions

  1. In a 16-word-deep asynchronous FIFO with 5-bit Gray code pointers, what is the correct condition for detecting full on the write side?
  2. In an asynchronous FIFO, the other side's pointer is used after synchronization, so the pointer value seen is 2–3 cycles stale. What effect does this delay have on full/empty detection?
  3. In an asynchronous FIFO with a 100 MHz write side and an 80 MHz read side, the write side writes a 100-word burst at one word per cycle and the read side reads one word per cycle. There is ample idle time between bursts. What is the minimum depth needed to avoid overflow (ignore synchronization delay)?
  4. The write side writes a 120-word burst at one word per cycle at 200 MHz. The read side, on a 150 MHz clock, reads one word in only 2 out of every 3 cycles. What is the minimum depth needed to avoid overflow (ignore synchronization delay)?
  5. The write side runs at 250 MHz and the read side at 200 MHz, both transferring one word per cycle. What is the minimum calculated depth for a FIFO receiving a 64-word burst (ignore synchronization delay and round up fractions)?