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Timing analysis and CDC

With a 2.0 ns clock at 50% duty cycle, a path launches on the rising edge and captures on the falling edge. With a setup time of 0.1 ns and zero skew, what is the maximum allowed sum of the clock-to-output delay and combinational logic delay?

  1. A1.9 ns
  2. B1.0 ns
  3. C0.9 ns
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Answer: C. 0.9 ns

A path launched on the rising edge and captured on the falling edge is called a half-cycle path. The capture edge comes half a period, 1.0 ns, after launch, so the allowed delay is 1.0 − 0.1 = 0.9 ns. 1.9 ns assumes a full period is available, and 1.0 ns forgets to subtract the setup time. A half-cycle path is tight for setup, but hold is checked against the falling edge half a period earlier, which gives a large hold margin.

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More Timing analysis and CDC questions

  1. With a 2.0 ns clock, a path runs from a flip-flop that launches data on the rising edge at time 0 to a latch that opens (becomes transparent) at 1.0 ns and closes at 2.0 ns. If the data arrives at the latch at 1.4 ns, how much time has been borrowed at this latch (time borrowing)?
  2. In a circuit that stops the clock with a two-input AND gate of the clock and an enable signal, what does the STA clock gating check verify?
  3. With a 2.0 ns clock, set_input_delay 0.6 ns is set on an input port. If the internal flip-flop's setup time is 0.1 ns and clock latency and skew are ignored, what is the maximum delay allowed for the on-chip path from the input port to the flip-flop?
  4. What does the value specified with set_output_delay represent?
  5. With a 2.5 ns (400 MHz) clock, set_output_delay 0.8 ns is set on an output port. If the clock-to-output delay of the flip-flop driving the port is 0.2 ns, what is the maximum delay allowed for the combinational logic and wiring from the flip-flop to the output port (ignore clock latency)?