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Timing analysis and CDC

In a circuit that stops the clock with a two-input AND gate of the clock and an enable signal, what does the STA clock gating check verify?

  1. AThat the enable signal changes at the same time as the rising clock edge
  2. BThat the enable signal changes only while the clock is 1
  3. CThat the enable signal does not change while the clock is 1 and finishes changing while the clock is 0
Show answer and explanation

Answer: C. That the enable signal does not change while the clock is 1 and finishes changing while the clock is 0

With an AND gate, if the enable changes while the clock is 1, the output clock can be cut short or a short pulse (glitch) can appear. STA therefore checks that the enable is stable before the rising clock edge (gating setup) and held until after the falling edge (gating hold). With a 2.0 ns period and 50% duty cycle, enable changes must fit within the 1.0 ns from the falling edge to the next rising edge. Using a clock gating cell with a built-in latch makes this easier to satisfy.

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  1. With a 2.0 ns clock, set_input_delay 0.6 ns is set on an input port. If the internal flip-flop's setup time is 0.1 ns and clock latency and skew are ignored, what is the maximum delay allowed for the on-chip path from the input port to the flip-flop?
  2. What does the value specified with set_output_delay represent?
  3. With a 2.5 ns (400 MHz) clock, set_output_delay 0.8 ns is set on an output port. If the clock-to-output delay of the flip-flop driving the port is 0.2 ns, what is the maximum delay allowed for the combinational logic and wiring from the flip-flop to the output port (ignore clock latency)?
  4. With a 1.0 ns clock, flip-flops are connected A→B→C. A→B needs 1.2 ns including clock-to-output delay and setup time, while 0.8 ns is enough for B→C. To meet setup on both by intentionally using skew, what should be done to B's clock (assume the clocks of A and C arrive at the same time)?
  5. When a clock is divided by two with a divider circuit and used for another circuit, how should it be handled in SDC?