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Timing analysis and CDC

In toggle synchronization (a scheme in which the sending side generates and passes a level signal that inverts each time a pulse arrives), how is the original pulse recovered on the receiving side?

  1. AUse the synchronized toggle signal directly as the pulse
  2. BAND the synchronized toggle signal with the receiving clock to make a one-cycle-wide pulse
  3. CXOR the synchronized toggle signal with a version of it delayed by one more stage
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Answer: C. XOR the synchronized toggle signal with a version of it delayed by one more stage

In toggle synchronization, the sending side inverts a flip-flop each time a pulse arrives, representing each event as a 0-to-1 or 1-to-0 transition. Being a level signal, it is not lost even if the pulse is shorter than the receiving period. On the receiving side, after two-stage synchronization, XORing with the value delayed by one more stage gives a one-cycle-wide pulse that is 1 only in the cycle where a change occurred. Using the toggle signal directly misses the second event, when it returns to 0. Logic operations with the clock cause glitches.

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  1. What constraint applies when passing pulses from a fast clock domain to a slow one with toggle synchronization?
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  3. Which is a drawback of transferring data between clock domains with a handshake?
  4. Why are the write and read pointers of an asynchronous FIFO converted to Gray code before being synchronized into the other domain?
  5. What is the 4-bit binary value 0110 (decimal 6) converted to Gray code?