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Timing analysis and CDC

In a synchronous circuit with a clock period of 2.0 ns, the launching flip-flop's clock-to-output delay is 0.2 ns, the combinational logic delay is 1.4 ns and the capturing flip-flop's setup time is 0.1 ns. With zero clock skew, what is the setup slack?

  1. A0.3 ns
  2. B0.4 ns
  3. C0.5 ns
Show answer and explanation

Answer: A. 0.3 ns

Setup slack is calculated as "required time − arrival time." The data arrival time is 0.2 + 1.4 = 1.6 ns and the required time is the next clock edge minus the setup time, 2.0 − 0.1 = 1.9 ns, so the slack is 1.9 − 1.6 = 0.3 ns. Being positive, it meets the constraint. 0.4 ns is the value obtained by forgetting to subtract the setup time, and 0.5 ns by adding the setup time instead. A negative slack means a violation.

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More Timing analysis and CDC questions

  1. On a flip-flop-to-flip-flop path, the clock-to-output delay is 0.15 ns, the maximum combinational logic delay is 2.2 ns and the setup time is 0.15 ns. Ignoring skew and clock uncertainty, what is the maximum clock frequency at which this path can operate?
  2. Which correctly describes WNS and TNS as they appear in STA reports?
  3. A path has a clock period of 1.0 ns, a clock-to-output delay of 0.1 ns, a combinational logic delay of 0.85 ns and a setup time of 0.08 ns. If the clock arrives at the capturing flip-flop 0.05 ns later than at the launching flip-flop, what is the setup slack?
  4. When the clock arrives at the capturing flip-flop later than at the launching flip-flop (positive skew), what is the effect on setup and hold?
  5. The launching flip-flop's minimum clock-to-output delay is 0.08 ns, the minimum combinational logic delay is 0.02 ns and the capturing flip-flop's hold time is 0.05 ns. If the clock arrives at the capturing flip-flop 0.1 ns later than at the launching flip-flop, what is the hold slack?