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Timing analysis and CDC

In STA, which combination correctly gives the corner conditions mainly used to check setup and hold?

  1. ASetup at the fast corner (fast transistors, high supply voltage), hold at the slow corner (slow transistors, low supply voltage)
  2. BSetup at the slow corner (slow transistors, low supply voltage), hold at the fast corner (fast transistors, high supply voltage)
  3. CChecking both only at the typical (typ) corner also covers variation in production parts
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Answer: B. Setup at the slow corner (slow transistors, low supply voltage), hold at the fast corner (fast transistors, high supply voltage)

Setup violations occur when data is too slow, so the slow corner, where delays are largest, is the worst case. Hold violations occur when data is too fast, so the fast corner, where delays are smallest, is the worst case. In practice clock path delays change at the same time, so both checks are run at multiple corners. In advanced processes, temperature inversion, where low temperature is slower, can occur, so the choice of temperature also needs care. typ alone cannot cover variation in production parts.

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More Timing analysis and CDC questions

  1. For OCV derating in setup analysis, the launch clock path and data path delays are multiplied by 1.1 and the capture clock path delay by 0.9. With a launch clock path of 1.0 ns, a data path (including clock-to-output) of 1.5 ns, a capture clock path of 1.0 ns (no common portion), a period of 3.0 ns and a setup time of 0.1 ns, what is the setup slack?
  2. In STA with OCV derating, when the launch and capture clock paths share a common portion, which correctly describes CRPR (common path pessimism removal)?
  3. In a circuit running on a 2.0 ns clock, a path has a data arrival time (clock-to-output plus combinational logic delay) of 3.3 ns and a setup time of 0.1 ns. Since this path only needs to capture once every two cycles, a setup multicycle path of 2 is set. What is the setup slack?
  4. When a setup multicycle path of N (N ≥ 2) is set, a hold multicycle path of N − 1 is normally set as well. Why?
  5. For which path is it appropriate to set a false path (set_false_path)?