Home Numbers Every Chip Engineer Should Know
The orders of magnitude worth carrying in your head, from silicon's band gap to DRAM latency. Each value links to a practice question with a full explanation. Values are typical figures; the notes give the conditions.
Test yourself: 10 questions
Materials & physics Devices & circuits Memory Lithography & fab Computer systems Interconnect & packaging Reliability & power
Materials & physics
Quantity Value Practice
Band gap of Si (300 K)Sets silicon's absorption edge near 1.1 µm. ≈ 1.12 eV Practice Band gap of Ge (room temp.)Absorption edge near 1.9 µm, useful for infrared detection. ≈ 0.66 eV Practice Band gap of GaAs (room temp.)A direct gap; GaAs emits near-infrared light at about 870 nm. ≈ 1.42 eV Practice Band gap of SiC / GaN4H-SiC, the power-device polytype, is about 3.26 eV. ≈ 3.3 eV / ≈ 3.4 eV Practice Thermal voltage kT/q (300 K)Precisely about 0.0259 V at 300 K. ≈ 26 mV Practice Intrinsic density ni of Si (room temp.)Sources quote 1.0–1.5×10¹⁰ cm⁻³. ≈ 1×10¹⁰ cm⁻³ Practice Electron / hole mobility in SiLightly doped silicon at room temperature; electrons are about three times faster. ≈ 1400 / ≈ 450 cm²/(V·s) Practice Lattice constant of SiDiamond-structure cubic cell holding eight atoms. ≈ 0.543 nm Practice Atomic density of SiA 1×10¹⁶ cm⁻³ dopant level is one atom in five million. ≈ 5×10²² cm⁻³ Practice Photon energy vs. wavelengthGaN's 3.4 eV corresponds to about 365 nm. E [eV] ≈ 1240 / λ [nm] Practice
Devices & circuits
Quantity Value Practice
Subthreshold swing limit (room temp.)Lowering Vth by ΔV multiplies subthreshold current by 10^(ΔV/S); at the ideal 60 mV/dec, 60 mV gives 10×. ≈ 60 mV/dec Practice Threshold voltage, advanced logicWith other conditions fixed, 0.1 V lower Vth raises subthreshold current by 10^(0.1 V / S): about 18× at S = 80 mV/dec. ≈ 0.2–0.4 V Practice Gate EOT, advanced devicesIncludes the interfacial layer; measured CET is somewhat larger. ≈ 0.8–1 nm Practice Relative permittivity: SiO₂ / HfO₂SiON is about 5–6 and Si3N4 about 7. ≈ 3.9 / ≈ 20–25 Practice Breakdown field of thermal SiO₂Devices run at a few MV/cm or less to last ten years. ≈ 10 MV/cm Practice Si diode forward voltage / BJT VBEVoltage at which a practical (mA-level) current flows at room temperature. ≈ 0.6–0.7 V Practice Diode VF / VBE temperature coefficientAt constant current; used in on-chip temperature sensors. ≈ −2 mV/°C Practice Ideal SNR of an N-bit ADC (full-scale sine)Quantization noise only, integrated from DC to fs/2. About 74 dB at 12 bits and 98 dB at 16 bits. ≈ 6.02N + 1.76 dB Practice
Memory
Quantity Value Practice
DRAM refresh window (DDR4, 0–85 °C)Every row is refreshed within this window; 32 ms at 85–95 °C. DDR5 uses 32 ms (16 ms when hot). Average command spacing tREFI ≈ 7.8 µs for DDR4. ≈ 64 ms Practice DRAM cell capacitance0 and 1 differ by only tens of thousands of electrons. ≈ 10 fF Practice Cell area: DRAM 1T1C vs. 6T SRAMDRAM packs roughly 20 times denser. ≈ 6F² vs. ≈ 120–150F² Practice NAND flash endurance (P/E cycles) SLC ≈ 100,000 · TLC a few thousand · QLC ≈ 1,000 Practice Flash data retention (example)Depends on product, wear and temperature: one SSD is rated 10 years at beginning of life but 1 year at end of life (25 °C). ≈ 10 years when new Practice
Lithography & fab
Quantity Value Practice
EUV wavelengthAbout 92 eV per photon, roughly 14 times ArF's photon energy. 13.5 nm Practice ArF excimer wavelength 193 nm (immersion NA up to 1.35) Practice EUV numerical apertureHigh-NA improves resolution about 1.7×. 0.33 → 0.55 (High-NA) Practice Standard wafer diameter / thicknessA 300 mm wafer weighs about 128 g. 300 mm / ≈ 775 µm Practice ISO Class 5 cleanroom limitEach class step is a factor of 10; room air is around Class 9. ≤ 100,000 particles (≥ 0.1 µm) per m³ Practice Melting point of SiThermal oxidation runs at about 800–1,200 °C. ≈ 1414 °C Practice Front-end cycle time, leading-edge logicOver a thousand process steps. ≈ 3 months or more Practice
Computer systems
Quantity Value Practice
Period of a 1 GHz clock 1 ns (light travels ≈ 30 cm) Practice L1 cache hitCapacity: tens of KB. ≈ 1 ns (a few cycles) Practice L2 cache hitL3 takes over ten ns (tens of cycles). a few ns Practice DRAM (main memory) accessHundreds of cycles for a CPU running at several GHz. ≈ 100 ns Practice SSD access ≈ tens to 100 µs Practice HDD accessSeek plus rotational delay; SSD random access is hundreds of times faster. several ms Practice Cache line sizeOne DDR4 BL8 burst on a 64-bit channel: 8 transfers × 8 bytes, excluding ECC. 64 bytes Practice Page size / huge page (x86-64)A 64-entry TLB would cover 256 KiB with 4 KiB pages or 128 MiB with 2 MiB pages; real TLB sizes differ by design. 4 KiB / 2 MiB Practice
Interconnect & packaging
Quantity Value Practice
Cu / Al resistivity (bulk, room temp.) ≈ 1.7 / ≈ 2.7 µΩ·cm Practice CTE: Si vs. organic substrateGlass/epoxy laminate below Tg; through-thickness CTE is much larger and low-CTE package laminates are lower. Si is about 2.6×10⁻⁶ /K. ≈ 3 vs. ≈ 15–17 ppm/K (in-plane) Practice Pitch: microbumps vs. hybrid bondingMicrobump pitches near 10 µm have been shown in research. Connection count scales with 1/pitch². typically tens of µm vs. < 10 µm Practice HBM3 bandwidth per stack6.4 Gb/s per pin. ≈ 819 GB/s (1,024-bit bus) Practice PCIe per-lane rate, Gen 3 → Gen 6Roughly doubles each generation. 8 → 16 → 32 → 64 GT/s Practice
Reliability & power
Quantity Value Practice
1 FIT 1 failure per 10⁹ device-hours Practice Typical design-life targetAlways tied to a stated junction temperature and duty cycle, e.g. 10 years continuous at Tj = 105 °C for some industrial processors. ≈ 10 years Practice Temperature rule of thumbHolds roughly near room temperature for Ea ≈ 0.5 eV. Lifetime ≈ ½ per +10 °C Practice ESD robustness target (human body model)Industry bodies now recommend 1 kV HBM for many ICs with proper ESD controls; use the device's qualification rating. ≈ 2 kV (common legacy target) Practice Max junction temp., Si power devicesDesigns typically operate around 125 °C for margin. 150–175 °C Practice Breakdown field of SiC ≈ 3 MV/cm (≈ 10× Si) Practice CMOS dynamic powerHalving the supply voltage cuts dynamic power to a quarter. P = αCV²f Practice
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