Timing analysis and CDC
When a clock is divided by two with a divider circuit and used for another circuit, how should it be handled in SDC?
- AThe divider output is treated as a data signal, so it is analyzed correctly without any definition
- BDefine the divider output as a generated clock, specifying its relationship to the source clock (divide-by-2)
- CDefine the divided clock as a new asynchronous clock unrelated to the source clock
Show answer and explanation
Answer: B. Define the divider output as a generated clock, specifying its relationship to the source clock (divide-by-2)
SDC is the timing constraint description that tells the tool the clock periods and waveforms, input/output delays, exception paths and so on. If nothing is defined, the divider output is not treated as a clock and the flip-flops beyond it are not analyzed correctly. Defined as a generated clock, it is analyzed as 250 MHz when the source clock is 500 MHz, including its phase relationship to the source clock. The two are synchronous, so treating them as asynchronous drops paths that should be checked from the analysis.