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Timing analysis and CDC

With a 2.0 ns clock, set_input_delay 0.6 ns is set on an input port. If the internal flip-flop's setup time is 0.1 ns and clock latency and skew are ignored, what is the maximum delay allowed for the on-chip path from the input port to the flip-flop?

  1. A1.3 ns
  2. B1.9 ns
  3. C1.4 ns
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Answer: A. 1.3 ns

set_input_delay specifies the time spent outside the chip from the clock edge until data reaches the input port, such as the external launching device's clock-to-output delay and the board trace delay. The on-chip path gets the remaining time: 2.0 − 0.6 − 0.1 = 1.3 ns. 1.9 ns ignores the input delay, and 1.4 ns forgets to subtract the setup time. Without a correctly specified input delay, paths from input ports are not analyzed correctly.

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More Timing analysis and CDC questions

  1. What does the value specified with set_output_delay represent?
  2. With a 2.5 ns (400 MHz) clock, set_output_delay 0.8 ns is set on an output port. If the clock-to-output delay of the flip-flop driving the port is 0.2 ns, what is the maximum delay allowed for the combinational logic and wiring from the flip-flop to the output port (ignore clock latency)?
  3. With a 1.0 ns clock, flip-flops are connected A→B→C. A→B needs 1.2 ns including clock-to-output delay and setup time, while 0.8 ns is enough for B→C. To meet setup on both by intentionally using skew, what should be done to B's clock (assume the clocks of A and C arrive at the same time)?
  4. When a clock is divided by two with a divider circuit and used for another circuit, how should it be handled in SDC?
  5. In a flip-flop with asynchronous reset, which STA check examines whether reset deassertion is too close to a clock edge?