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Timing analysis and CDC

Which is a correct precaution about the connection between the first and second stages of a two-flip-flop synchronizer?

  1. AThe first-stage output may branch to other circuits in addition to the second stage
  2. BInsert no combinational logic; place the two flip-flops close together and connect them directly
  3. CInsert several delay buffers between the first and second stages to add timing margin
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Answer: B. Insert no combinational logic; place the two flip-flops close together and connect them directly

The first-stage flip-flop can go metastable, and the idea of a synchronizer is to secure time for its output to resolve in the interval up to the second stage's setup. Any combinational logic or buffers in between reduce the resolution time by their delay, degrading MTBF exponentially. Branching the first-stage output to other circuits lets the unstable value be used directly, and different destinations may interpret it as different values. Placement is also often constrained to keep the two close together.

Two-flip-flop synchronizer Source clock domain Destination clock domain Source FF FF1 FF2 Async Direct Synced output Source clock Dest. clock Metastable risk Dest. clock FF1 output Unsettled FF2 output ~1 cycle If FF1 settles before the next edge, FF2 gets the correct value
Two-flip-flop synchronizer · View in diagrams
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More Timing analysis and CDC questions

  1. Why must the output of combinational logic in the sending clock domain not be fed directly into a synchronizer in the receiving domain?
  2. Each bit of 4-bit data is passed to another clock domain through its own two-stage synchronizer. What problem can occur when the data changes from 0111 to 1000?
  3. Which is a correct way to pass multi-bit data safely to another clock domain?
  4. A pulse that is 1 for only one cycle (2 ns) in a 500 MHz clock domain is passed to a 100 MHz domain through a two-stage synchronizer. What problem can occur?
  5. To pass a level signal reliably from a 400 MHz domain to a 100 MHz domain through a synchronizer, the signal width should be at least 1.5 times the receiving clock period. What is the minimum width in sending-clock cycles?