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Timing analysis and CDC

In an asynchronous FIFO, the other side's pointer is used after synchronization, so the pointer value seen is 2–3 cycles stale. What effect does this delay have on full/empty detection?

  1. AIt only delays the deassertion of full and empty; neither overflow nor reading from an empty FIFO occurs
  2. BFull detection is delayed, so too much may be written and data may overflow
  3. CEmpty detection is delayed, so the FIFO may be read while empty
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Answer: A. It only delays the deassertion of full and empty; neither overflow nor reading from an empty FIFO occurs

The read pointer seen by the write side is stale, so reading appears less advanced than it actually is, and the FIFO is judged to be fuller than it really is. In other words, full is always asserted when the FIFO is truly full; only its deassertion after space frees up is slightly delayed. The same goes for empty on the read side: newly written data just becomes visible later. Both err on the safe (pessimistic) side, so data is not corrupted, but extra depth is provided to maintain performance despite the delay.

Asynchronous FIFO structure Write side (wclk) Read side (rclk) Dual-port RAM R/W on two clocks Write data Write pointer To Gray code Read data Read pointer To Gray code 2-FF sync Empty check 2-FF sync Full check Gray-code pointer In Gray code, only 1 bit changes per increment
Asynchronous FIFO structure · View in diagrams
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More Timing analysis and CDC questions

  1. In an asynchronous FIFO with a 100 MHz write side and an 80 MHz read side, the write side writes a 100-word burst at one word per cycle and the read side reads one word per cycle. There is ample idle time between bursts. What is the minimum depth needed to avoid overflow (ignore synchronization delay)?
  2. The write side writes a 120-word burst at one word per cycle at 200 MHz. The read side, on a 150 MHz clock, reads one word in only 2 out of every 3 cycles. What is the minimum depth needed to avoid overflow (ignore synchronization delay)?
  3. The write side runs at 250 MHz and the read side at 200 MHz, both transferring one word per cycle. What is the minimum calculated depth for a FIFO receiving a 64-word burst (ignore synchronization delay and round up fractions)?
  4. Which is the correct structure of a reset synchronizer that generates, from an active-low external reset, an internal reset that is "asserted asynchronously and deasserted synchronously"?
  5. Two control signals from the same sending domain are each received through a separate two-stage synchronizer and ANDed on the receiving side. What is the problem with this design?