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Timing analysis and CDC

With a 2.0 ns clock, a path runs from a flip-flop that launches data on the rising edge at time 0 to a latch that opens (becomes transparent) at 1.0 ns and closes at 2.0 ns. If the data arrives at the latch at 1.4 ns, how much time has been borrowed at this latch (time borrowing)?

  1. A0.6 ns
  2. B0.4 ns
  3. C1.4 ns
Show answer and explanation

Answer: B. 0.4 ns

A latch passes its input straight through while open, so data arriving after the opening edge is still captured correctly as long as it arrives before the latch closes. The 1.4 − 1.0 = 0.4 ns used beyond the opening edge (1.0 ns) is the borrowed time, and the time available to the next stage is reduced by that amount. 0.6 ns is the time remaining until closing, and 1.4 ns is the arrival time itself. Borrowing is limited to the closing edge minus the latch setup time.

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More Timing analysis and CDC questions

  1. In a circuit that stops the clock with a two-input AND gate of the clock and an enable signal, what does the STA clock gating check verify?
  2. With a 2.0 ns clock, set_input_delay 0.6 ns is set on an input port. If the internal flip-flop's setup time is 0.1 ns and clock latency and skew are ignored, what is the maximum delay allowed for the on-chip path from the input port to the flip-flop?
  3. What does the value specified with set_output_delay represent?
  4. With a 2.5 ns (400 MHz) clock, set_output_delay 0.8 ns is set on an output port. If the clock-to-output delay of the flip-flop driving the port is 0.2 ns, what is the maximum delay allowed for the combinational logic and wiring from the flip-flop to the output port (ignore clock latency)?
  5. With a 1.0 ns clock, flip-flops are connected A→B→C. A→B needs 1.2 ns including clock-to-output delay and setup time, while 0.8 ns is enough for B→C. To meet setup on both by intentionally using skew, what should be done to B's clock (assume the clocks of A and C arrive at the same time)?