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Timing analysis and CDC

On a flip-flop-to-flip-flop path, the clock-to-output delay is 0.15 ns, the maximum combinational logic delay is 2.2 ns and the setup time is 0.15 ns. Ignoring skew and clock uncertainty, what is the maximum clock frequency at which this path can operate?

  1. AAbout 425 MHz
  2. BAbout 455 MHz
  3. C400 MHz
Show answer and explanation

Answer: C. 400 MHz

The minimum clock period is the sum of the clock-to-output delay, the combinational logic delay and the setup time. 0.15 + 2.2 + 0.15 = 2.5 ns, so the maximum frequency is 1 ÷ 2.5 ns = 400 MHz. About 425 MHz comes from 2.35 ns, which leaves out the setup time, and about 455 MHz from the 2.2 ns combinational logic delay alone. The maximum frequency of the whole chip is set by the tightest of such paths, the critical path.

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More Timing analysis and CDC questions

  1. Which correctly describes WNS and TNS as they appear in STA reports?
  2. A path has a clock period of 1.0 ns, a clock-to-output delay of 0.1 ns, a combinational logic delay of 0.85 ns and a setup time of 0.08 ns. If the clock arrives at the capturing flip-flop 0.05 ns later than at the launching flip-flop, what is the setup slack?
  3. When the clock arrives at the capturing flip-flop later than at the launching flip-flop (positive skew), what is the effect on setup and hold?
  4. The launching flip-flop's minimum clock-to-output delay is 0.08 ns, the minimum combinational logic delay is 0.02 ns and the capturing flip-flop's hold time is 0.05 ns. If the clock arrives at the capturing flip-flop 0.1 ns later than at the launching flip-flop, what is the hold slack?
  5. A hold violation (slack −0.03 ns) is found on an ordinary path that launches and captures on the rising edge of the same clock. How is this violation affected if the clock frequency is halved?