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Timing analysis and CDC

What does the value specified with set_output_delay represent?

  1. AThe upper limit on the delay from an internal flip-flop to the output port
  2. BThe time needed outside the chip from when data leaves the output port until it is captured by the receiving device
  3. CThe amount of current the output port can drive
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Answer: B. The time needed outside the chip from when data leaves the output port until it is captured by the receiving device

set_output_delay specifies the time consumed outside the chip, referenced to the clock edge. For example, if the board trace delay is 0.3 ns and the receiving device's setup time is 0.7 ns, the output delay is set to 1.0 ns, and STA checks the path from the internal flip-flop to the output port against the time left after subtracting this value from the period. The upper limit on internal delay results from this constraint; it is not a value specified directly. Drive current is a separate matter from timing constraints.

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More Timing analysis and CDC questions

  1. With a 2.5 ns (400 MHz) clock, set_output_delay 0.8 ns is set on an output port. If the clock-to-output delay of the flip-flop driving the port is 0.2 ns, what is the maximum delay allowed for the combinational logic and wiring from the flip-flop to the output port (ignore clock latency)?
  2. With a 1.0 ns clock, flip-flops are connected A→B→C. A→B needs 1.2 ns including clock-to-output delay and setup time, while 0.8 ns is enough for B→C. To meet setup on both by intentionally using skew, what should be done to B's clock (assume the clocks of A and C arrive at the same time)?
  3. When a clock is divided by two with a divider circuit and used for another circuit, how should it be handled in SDC?
  4. In a flip-flop with asynchronous reset, which STA check examines whether reset deassertion is too close to a clock edge?
  5. Which path between two clock domains requires a synchronizer?