Timing analysis and CDC

A path has a clock period of 1.0 ns, a clock-to-output delay of 0.1 ns, a combinational logic delay of 0.85 ns and a setup time of 0.08 ns. If the clock arrives at the capturing flip-flop 0.05 ns later than at the launching flip-flop, what is the setup slack?

  1. A−0.03 ns
  2. B+0.02 ns
  3. C−0.08 ns
Show answer and explanation

Answer: B. +0.02 ns

When the capture clock arrives late (positive skew), the capturing edge shifts later, giving more time for setup. The required time is 1.0 + 0.05 − 0.08 = 0.97 ns and the arrival time is 0.1 + 0.85 = 0.95 ns, so the slack is +0.02 ns. −0.03 ns ignores the skew, and −0.08 ns treats the skew in the opposite direction (as if the capture clock arrived early). Note that the same skew works against hold.

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More Timing analysis and CDC questions

  1. When the clock arrives at the capturing flip-flop later than at the launching flip-flop (positive skew), what is the effect on setup and hold?
  2. The launching flip-flop's minimum clock-to-output delay is 0.08 ns, the minimum combinational logic delay is 0.02 ns and the capturing flip-flop's hold time is 0.05 ns. If the clock arrives at the capturing flip-flop 0.1 ns later than at the launching flip-flop, what is the hold slack?
  3. A hold violation (slack −0.03 ns) is found on an ordinary path that launches and captures on the rising edge of the same clock. How is this violation affected if the clock frequency is halved?
  4. To fix a hold violation, delay buffers are inserted in the data path. What is the most important thing to check when doing this?
  5. On a path with a clock period of 1.25 ns (800 MHz), the clock-to-output delay plus combinational logic delay totals 1.05 ns, the setup time is 0.05 ns, and the setup clock uncertainty is set to 0.05 ns. What is the setup slack?