Enter the phase-noise values from a clock or oscillator datasheet to integrate them over a chosen band and get the RMS phase fluctuation and the RMS timing fluctuation, or jitter. You can see which offset frequencies dominate the jitter and how it changes with the integration band and the carrier frequency.
Results
The upper limit of the integration band must be larger than the lower limit.
Integrated phase noise (single-sideband)
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RMS phase error φ
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RMS phase error φ (degrees)
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RMS jitter φ/(2π·f0)
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The horizontal axis is logarithmic. The blue line is the phase noise inside the integration band; the thin dashed lines are the parts outside it and the lower and upper limits of the band.
Segment (offset frequency)
Contribution to φ²
1 kHz – 10 kHz
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10 kHz – 100 kHz
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100 kHz – 1 MHz
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1 MHz – 10 MHz
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10 MHz – 20 MHz
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Outside the points (end values extended)
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Phase noise is taken as the single-sideband spectrum L(f). Between points the dB value is assumed to change linearly with log f (noise power follows a power of f), and each segment is integrated in closed form. With A the integrated value, the RMS phase error is φ = √(2A) rad and the RMS jitter is φ/(2π·f0). Below 1 kHz and above 20 MHz the end values are assumed to continue flat. Spurs (unwanted tones at specific frequencies) are not included.
See it as a graph
Other inputs stay at their current values while the chosen input varies from 1/4 to 4 times its current value. The red dot is the current value.
How phase noise relates to jitter
Phase noise L(f) is the noise power in a 1 Hz bandwidth at an offset f from the carrier, relative to the carrier power, in dBc/Hz. If A is its integral over a chosen band, the RMS phase fluctuation including both sidebands is φ = √(2A) radians. One period 1/f0 corresponds to 2π radians, so the RMS jitter in time is φ/(2π·f0). For the default 100 MHz clock, A = −73.4 dBc and φ = 0.301 mrad, giving a jitter of about 479 fs.
Segment integration and the −10 dB/dec case
If the phase noise between points is a straight line on a log-frequency axis, the noise power in each segment follows a power of f and can be integrated in closed form. Only a segment falling at −10 dB/dec (1/f) integrates to a logarithm, so every decade of it contributes equally. In segments falling faster than −10 dB/dec the low-frequency end dominates the integral; in gentler or flat segments the high-frequency end dominates. With the defaults, 12 kHz to 100 kHz accounts for about 46.8% of φ² and 100 kHz to 1 MHz for about 30.2%.
Integration band and carrier frequency
Jitter depends strongly on the integration band, so datasheets always state it. The 12 kHz to 20 MHz band comes from SONET optical networking standards and is widely used to compare clocks. Widening the lower limit of the default to 1 kHz raises the jitter to about 596 fs. With the same phase noise, doubling f0 halves the jitter to about 240 fs. Conversely, multiplying a frequency by N in a PLL ideally raises the phase noise by 20·log₁₀N dB, so the jitter in time stays the same.
How jitter affects performance
In an ADC, a sampling-time error turns the signal's change during that time into an error, so jitter tj limits SNR to −20·log₁₀(2π·fin·tj). With the default of about 479 fs, the limit for a 100 MHz input is about 70.4 dB. In high-speed serial links, jitter narrows the horizontal opening of the eye diagram. The RMS jitter computed here describes the random component; estimating bit error rate requires converting it to a peak value, and deterministic jitter from spurs must be considered separately.
CBecause the faster the signal changes, the larger the voltage error caused by a tiny shift in sampling time
Show answer and explanation
Answer: C. Because the faster the signal changes, the larger the voltage error caused by a tiny shift in sampling time
If the sampling instant shifts by Δt, the signal's change during that time becomes error. Since a sine wave's slope is proportional to frequency, jitter limits SNR to −20 log₁₀(2πf·tj). Achieving 70 dB on a 100 MHz signal, for example, requires jitter below about 0.5 ps. In high-speed, high-resolution ADCs and radio receivers, a low-phase-noise clock source is therefore decisive.
A PLL consists of a phase detector, loop filter, voltage-controlled oscillator (VCO) and divider, steering the VCO so that its divided output stays in phase with the reference clock. A divide ratio of N yields N times the reference frequency, so a 25 MHz crystal can produce a multi-GHz CPU clock. Fractional-N division synthesizes fine frequency steps, and PLLs also serve as radio local oscillators and for clock recovery in high-speed serial links.
ABecause the hold check is performed only at falling clock edges
BBecause jitter occurs only at high frequencies, and hold analysis is done at a lowered frequency
CBecause hold compares against the same clock edge, so variation in the edge timing affects the launching and capturing sides equally and cancels out
Show answer and explanation
Answer: C. Because hold compares against the same clock edge, so variation in the edge timing affects the launching and capturing sides equally and cancels out
Period jitter is variation in the interval between one edge and the next. Setup is judged on the interval between the launching edge and the next edge, so with ±30 ps of jitter on a 1.0 ns period, the available time shrinks to 0.97 ns in the worst case. Hold compares launch and capture at the same edge, so whether that edge is early or late, both sides move together and the effect of jitter almost cancels out. However, the estimate of skew before the clock tree is built is included in the hold uncertainty as well.
AIt overlays the waveforms of many bits; the wider and taller the central "eye" opening, the more margin there is
BThe more closed the eye, the better the signal
CIt is a chart for checking the health of human eyes
Show answer and explanation
Answer: A. It overlays the waveforms of many bits; the wider and taller the central "eye" opening, the more margin there is
An eye diagram slices the waveform at each bit period and overlays the pieces. An eye-shaped gap appears between the 0 and 1 traces; its height represents the margin against noise and its width the margin against timing variation (jitter). Channel loss, reflections and jitter close the eye. The receiver decides bits at the center of the eye, so its opening is a measure of quality.
FAQ
How much does jitter drop if phase noise improves by 10 dB?
If the phase noise falls by 10 dB at every offset, the integrated value A drops to 1/10 and the phase error and jitter fall by 1/√10, to about 0.316 times. If only some segments improve, jitter falls according to their share of φ², so it is most effective to improve the segments that contribute most.
How should the integration band be chosen?
Choose the band that affects the circuit using the clock. Slow phase changes below the lower limit can often be tracked out by the receiver's PLL or CDR, and the upper limit is set by the signal bandwidth or later filtering. Communication standards often specify the band, and jitter values quoted over different bands cannot be compared directly.
Are phase jitter, period jitter and cycle-to-cycle jitter the same?
No. Phase noise gives the RMS deviation of each edge from an ideal clock, called phase jitter. Period jitter is the variation in the length of one period, and cycle-to-cycle jitter is the difference between adjacent periods; timing analysis usually uses these. The values differ for the same clock, so check which definition is meant.