Timing analysis and CDC

In a flip-flop with asynchronous reset, which STA check examines whether reset deassertion is too close to a clock edge?

  1. AClock gating check
  2. BRecovery and removal checks
  3. CMaximum transition (max transition) check
Show answer and explanation

Answer: B. Recovery and removal checks

Like a data input, deassertion of an asynchronous reset must be a certain time away from the clock edge. The recovery check (equivalent to setup) looks at whether deassertion comes too soon before the edge, and the removal check (equivalent to hold) at whether it comes too soon after the edge. A violation makes it uncertain whether reset is released in that cycle, so different flip-flops may start operating in different cycles. The transition check looks at the slew of signal waveforms and serves a different purpose.

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More Timing analysis and CDC questions

  1. Which path between two clock domains requires a synchronizer?
  2. How does the mean time between failures (MTBF) due to metastability change when a two-flip-flop synchronizer is extended to three stages?
  3. Raising the clock frequency on the receiving side of a synchronizer shortens MTBF. Why?
  4. Which is a correct precaution about the connection between the first and second stages of a two-flip-flop synchronizer?
  5. Why must the output of combinational logic in the sending clock domain not be fed directly into a synchronizer in the receiving domain?