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Timing analysis and CDC

To pass a level signal reliably from a 400 MHz domain to a 100 MHz domain through a synchronizer, the signal width should be at least 1.5 times the receiving clock period. What is the minimum width in sending-clock cycles?

  1. A4 cycles
  2. B6 cycles
  3. C15 cycles
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Answer: B. 6 cycles

The receiving period is 1 ÷ 100 MHz = 10 ns, and 1.5 times that is 15 ns. The sending period is 1 ÷ 400 MHz = 2.5 ns, so a width of at least 15 ÷ 2.5 = 6 cycles is needed. 4 cycles (10 ns) is exactly one receiving period; if both the start and end of the signal fall right at edges, both captures can fail and the signal can be missed. With 1.5 times, there is always at least one edge that captures a stable value. 15 cycles confuses ns with cycles.

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