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Timing analysis and CDC

Raising the clock frequency on the receiving side of a synchronizer shortens MTBF. Why?

  1. ABecause raising the clock frequency lengthens the flip-flop's setup time
  2. BBecause raising the clock frequency reduces how often the sending side's data changes
  3. CBecause there are more captures and, with a shorter period, less time is available for metastability to resolve
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Answer: C. Because there are more captures and, with a shorter period, less time is available for metastability to resolve

In the MTBF equation, the receiving clock frequency f_clk is in the denominator, so the chance of hitting a dangerous moment grows in proportion to the number of captures. In addition, the resolution time t_r is largely set by the period, so raising the frequency reduces t_r and sharply reduces the exponential term e^(t_r/τ). For example, going from 500 MHz to 1 GHz cuts the period from 2 ns to 1 ns, and MTBF shrinks by far more than a simple factor of two. This is why three-stage synchronizers are used with fast clocks.

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  1. Which is a correct precaution about the connection between the first and second stages of a two-flip-flop synchronizer?
  2. Why must the output of combinational logic in the sending clock domain not be fed directly into a synchronizer in the receiving domain?
  3. Each bit of 4-bit data is passed to another clock domain through its own two-stage synchronizer. What problem can occur when the data changes from 0111 to 1000?
  4. Which is a correct way to pass multi-bit data safely to another clock domain?
  5. A pulse that is 1 for only one cycle (2 ns) in a 500 MHz clock domain is passed to a 100 MHz domain through a two-stage synchronizer. What problem can occur?