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Timing analysis and CDC

The launching flip-flop's minimum clock-to-output delay is 0.08 ns, the minimum combinational logic delay is 0.02 ns and the capturing flip-flop's hold time is 0.05 ns. If the clock arrives at the capturing flip-flop 0.1 ns later than at the launching flip-flop, what is the hold slack?

  1. A+0.05 ns (met)
  2. B+0.15 ns (met)
  3. C−0.05 ns (violated)
Show answer and explanation

Answer: C. −0.05 ns (violated)

Hold slack is "arrival time − required time" and checks whether data arrives too early. The minimum data arrival time is 0.08 + 0.02 = 0.10 ns and the required time is the capture clock arrival of 0.1 ns plus the 0.05 ns hold time, 0.15 ns, so the slack is 0.10 − 0.15 = −0.05 ns, a violation. +0.05 ns ignores the skew, and +0.15 ns adds the skew in the favorable direction. This violation is common on paths with little logic in between, such as shift registers.

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More Timing analysis and CDC questions

  1. A hold violation (slack −0.03 ns) is found on an ordinary path that launches and captures on the rising edge of the same clock. How is this violation affected if the clock frequency is halved?
  2. To fix a hold violation, delay buffers are inserted in the data path. What is the most important thing to check when doing this?
  3. On a path with a clock period of 1.25 ns (800 MHz), the clock-to-output delay plus combinational logic delay totals 1.05 ns, the setup time is 0.05 ns, and the setup clock uncertainty is set to 0.05 ns. What is the setup slack?
  4. In clock uncertainty settings, period jitter is often included for setup but not for hold. Why?
  5. In STA, which combination correctly gives the corner conditions mainly used to check setup and hold?