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Timing analysis and CDC

Two control signals from the same sending domain are each received through a separate two-stage synchronizer and ANDed on the receiving side. What is the problem with this design?

  1. AMetastability is amplified through the AND gate, and the entire receiving circuit remains unstable
  2. BTwo signals that changed simultaneously on the sending side may appear one cycle apart on the receiving side, producing a combination that should be impossible
  3. CThe two signals are always aligned to the same cycle on the receiving side, so no problem occurs
Show answer and explanation

Answer: B. Two signals that changed simultaneously on the sending side may appear one cycle apart on the receiving side, producing a combination that should be impossible

Separately synchronized signals merging again on the receiving side is called reconvergence. Even if the two signals change simultaneously on the sending side, whether each synchronizer resolves to the old or new value is independent, so a cycle in which only one of them has changed can occur on the receiving side. For example, if the two change 0→1 and 1→0 simultaneously, the AND should be 0 both before and after, yet a 1 can appear for one cycle. The remedies are to synchronize them as a single signal and then split it, or to use an encoding in which only one bit changes, such as Gray code.

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More Timing analysis and CDC questions

  1. Why is checking with a CDC verification tool considered necessary even when STA and RTL simulation have been done?
  2. Why can it be a problem to leave the paths that carry an asynchronous FIFO's Gray code pointers to the other domain unconstrained (false path) just because they are asynchronous?
  3. In a synchronous circuit with a clock period of 2.0 ns, the launching flip-flop's clock-to-output delay is 0.2 ns, the combinational logic delay is 1.4 ns and the capturing flip-flop's setup time is 0.1 ns. With zero clock skew, what is the setup slack?
  4. On a flip-flop-to-flip-flop path, the clock-to-output delay is 0.15 ns, the maximum combinational logic delay is 2.2 ns and the setup time is 0.15 ns. Ignoring skew and clock uncertainty, what is the maximum clock frequency at which this path can operate?
  5. Which correctly describes WNS and TNS as they appear in STA reports?