English
Menu

Timing analysis and CDC

The write side runs at 250 MHz and the read side at 200 MHz, both transferring one word per cycle. What is the minimum calculated depth for a FIFO receiving a 64-word burst (ignore synchronization delay and round up fractions)?

  1. A51 words
  2. B64 words
  3. C13 words
Show answer and explanation

Answer: C. 13 words

Writing 64 words takes 64 × 4 ns = 256 ns, during which 256 ÷ 5 ns = 51.2 words' worth can be read. The remainder is 64 − 51.2 = 12.8 words, so rounding up, 13 words are needed. 51 words is the amount that can be read, and 64 words is the value for buffering the entire burst, which is enough but not the minimum. In actual designs, margin for pointer synchronization delay is added and the depth is rounded up to a power of two such as 16 words, which suits Gray code pointers.

Practice this topic Back to topic

Books on Timing analysis and CDC Ad

As an Amazon Associate I earn from qualifying purchases.

More Timing analysis and CDC questions

  1. Which is the correct structure of a reset synchronizer that generates, from an active-low external reset, an internal reset that is "asserted asynchronously and deasserted synchronously"?
  2. Two control signals from the same sending domain are each received through a separate two-stage synchronizer and ANDed on the receiving side. What is the problem with this design?
  3. Why is checking with a CDC verification tool considered necessary even when STA and RTL simulation have been done?
  4. Why can it be a problem to leave the paths that carry an asynchronous FIFO's Gray code pointers to the other domain unconstrained (false path) just because they are asynchronous?
  5. In a synchronous circuit with a clock period of 2.0 ns, the launching flip-flop's clock-to-output delay is 0.2 ns, the combinational logic delay is 1.4 ns and the capturing flip-flop's setup time is 0.1 ns. With zero clock skew, what is the setup slack?