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Timing analysis and CDC

Why is checking with a CDC verification tool considered necessary even when STA and RTL simulation have been done?

  1. ABecause CDC verification tools calculate setup and hold for every flip-flop more accurately than STA
  2. BBecause a CDC verification tool can automatically convert asynchronous clocks into synchronous ones
  3. CBecause STA excludes paths between asynchronous clocks from analysis and RTL simulation does not reproduce metastability, so synchronization errors are not found
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Answer: C. Because STA excludes paths between asynchronous clocks from analysis and RTL simulation does not reproduce metastability, so synchronization errors are not found

STA cannot determine timing on paths between asynchronous clocks, so they are normally excluded from analysis, for example by specifying clock groups. In RTL simulation, flip-flops always resolve to 0 or 1, so the design appears to work correctly even without synchronizers. CDC verification tools examine the circuit structure and find paths without synchronizers, combinational logic in front of synchronizers, individually synchronized multi-bit signals, reconvergence and so on. Timing calculation is the job of STA.

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More Timing analysis and CDC questions

  1. Why can it be a problem to leave the paths that carry an asynchronous FIFO's Gray code pointers to the other domain unconstrained (false path) just because they are asynchronous?
  2. In a synchronous circuit with a clock period of 2.0 ns, the launching flip-flop's clock-to-output delay is 0.2 ns, the combinational logic delay is 1.4 ns and the capturing flip-flop's setup time is 0.1 ns. With zero clock skew, what is the setup slack?
  3. On a flip-flop-to-flip-flop path, the clock-to-output delay is 0.15 ns, the maximum combinational logic delay is 2.2 ns and the setup time is 0.15 ns. Ignoring skew and clock uncertainty, what is the maximum clock frequency at which this path can operate?
  4. Which correctly describes WNS and TNS as they appear in STA reports?
  5. A path has a clock period of 1.0 ns, a clock-to-output delay of 0.1 ns, a combinational logic delay of 0.85 ns and a setup time of 0.08 ns. If the clock arrives at the capturing flip-flop 0.05 ns later than at the launching flip-flop, what is the setup slack?